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16 lines
374 B
Plaintext
16 lines
374 B
Plaintext
Veryl is a modern hardware description language.
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This project is under the exploration phase of language design.
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Features:
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* Symplified syntax
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* Based on SystemVerilog / Rust
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* Transpiler to SystemVerilog
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* Human readable output
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* Interoperability with SystemVerilog
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* Integrated Tools
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* Semantic checker
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* Source code formatter
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* Language server
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