1
0
mirror of https://git.FreeBSD.org/ports.git synced 2024-12-03 01:23:49 +00:00
freebsd-ports/cad/p5-Verilog-Perl/pkg-plist
Sylvio Cesar Teixeira 913a43d5b5 - Update to 3.251
PR:		ports/148726
Submitted by:	Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer)
2010-07-23 14:33:24 +00:00

37 lines
1.7 KiB
Plaintext

bin/vhier
bin/vpassert
bin/vppreproc
bin/vrename
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/EditFiles.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Getopt.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Language.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Cell.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Defparam.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/File.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Interface.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Logger.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ModPort.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Module.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Net.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Pin.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Port.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Subclass.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Parser.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Preproc.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/SigParser.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Std.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Verilog-Perl.pod
%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Language/.packlist
%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser/Parser.bs
%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser/Parser.so
%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc/Preproc.bs
%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc/Preproc.so
@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc
@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser
@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Language
@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog
@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist
@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/Verilog