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mirror of https://git.FreeBSD.org/ports.git synced 2024-11-19 00:13:33 +00:00
freebsd-ports/cad
2024-03-06 02:32:59 -08:00
..
abc
admesh
adms
alliance
antimony
apio
appcsxcad
archimedes
astk-client
astk-serveur
atlc
brlcad
calculix
calculix-ccx
camotics
caneda
cascade
cascade-compiler
chipvault
csxcad
cura
cura-engine
cvc
digital
dinotrace
ecpprog
electric
electric-ng
fasm
fdm_materials
feappv
fidocadj
freecad
freehdl
fritzing
gds3d
gdscpp
gdsreader
gdstk
gdt
geda cad/geda: Move man pages to share/man 2024-03-02 23:32:29 +00:00
gerbv
ghdl
gmsh
gnucap
gplcver
graywolf
gspiceui
gtkwave
horizon-eda
hs-verismith
ifcopenshell
impact
irsim
iverilog cad/iverilog: Move man pages to share/man 2024-03-02 23:32:29 +00:00
k40-whisperer
kicad
kicad-devel
kicad-doc
kicad-library-footprints
kicad-library-footprints-devel
kicad-library-packages3d
kicad-library-packages3d-devel
kicad-library-symbols
kicad-library-symbols-devel
kicad-library-templates
kicad-library-templates-devel
klayout
ktechlab
ldraw
ldview
leocad cad/leocad: Move man pages to share/man 2024-03-02 23:32:29 +00:00
lepton-eda
libgdsii
libopencad
librecad
libredwg
librepcb
librnd
logisim
magic
meshdev
meshlab
netgen
netgen-lvs
ngspice_rework cad/ngspice_rework: Move man pages to share/man 2024-03-02 23:32:29 +00:00
nvc cad/nvc: Move man pages to share/man 2024-03-02 23:37:53 +00:00
opencascade
opencascade740
openctm
openfpgaloader
openroad
openscad
openscad-devel
opentimer
openvsp
oregano
p5-GDS2
p5-Verilog-Perl
padring
pcb cad/pcb: Move man pages to share/man 2024-03-02 23:44:56 +00:00
pcb-rnd
pdnmesh
PrusaSlicer cad/PrusaSlicer: Mark BROKEN 2024-03-03 20:26:10 +01:00
py-amaranth
py-cocotb
py-edalize
py-ezdxf
py-gdspy
py-gdstk
py-gmsh
py-lcapy
py-phidl
py-pyfda
py-pygmsh
py-pymtl
py-pyvcd
py-vunit-hdl
python-gdsii
qcad
qcsxcad
qelectrotech
qflow
qmls
qrouter
qspeakers
qucs-s
qucsator
repsnapper
rubygem-gdsii
scotch
silice
solvespace
sp2sp
spice cad/spice: Move man pages to share/man 2024-03-02 23:54:43 +00:00
stepcode
stm32flash
sumo
surelog
svlint
svls
sweethome3d
symbiyosys
tkgate
tochnog
uhdm
uranium
verilator
verilog-mode.el
veroroute
veryl cad/veryl: update 0.7.0 → 0.7.1 2024-03-06 02:32:58 -08:00
xcircuit cad/xcircuit: Move man pages to share/man 2024-03-03 00:05:21 +00:00
xyce science/trilinos: update 13-4-1 → 15-1-0 2024-03-06 02:32:59 -08:00
yosys
yosys-ghdl-plugin
yosys-systemverilog
z88
zcad
Makefile