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64 lines
1.7 KiB
Makefile
64 lines
1.7 KiB
Makefile
PORTNAME= yosys
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DISTVERSIONPREFIX= yosys-
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DISTVERSION= 0.43
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CATEGORIES= cad
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MAINTAINER= yuri@FreeBSD.org
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COMMENT= Yosys Open SYnthesis Suite
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WWW= https://yosyshq.net/yosys/
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LICENSE= ISCL
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LICENSE_FILE= ${WRKSRC}/COPYING
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BUILD_DEPENDS= abc:cad/abc \
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bash:shells/bash \
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gawk:lang/gawk
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LIB_DEPENDS= libffi.so:devel/libffi
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RUN_DEPENDS= xdot:x11/py-xdot@${PY_FLAVOR} \
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bash:shells/bash
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TEST_DEPENDS= iverilog:cad/iverilog
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USES= bison compiler:c++11-lang gmake pkgconfig python readline \
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shebangfix tcl
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SHEBANG_FILES= backends/smt2/smtbmc.py \
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misc/yosys-config.in
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SHEBANG_GLOB= *.sh *.py
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USE_GITHUB= yes
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GH_ACCOUNT= YosysHQ
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BINARY_ALIAS= python3=${PYTHON_CMD} tclsh=${TCLSH}
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MAKE_ARGS= ABCEXTERNAL=abc
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MAKE_ENV= MAKE=${GMAKE}
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TEST_TARGET= test # some tests fail, see https://github.com/YosysHQ/yosys/issues/3731
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OPTIONS_GROUP= SOLVERS
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OPTIONS_GROUP_SOLVERS= CVC5 YICES Z3
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OPTIONS_DEFINE= TCMALLOC
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OPTIONS_DEFAULT= TCMALLOC YICES # YICES: same as the default in C++ code ; TCMALLOC: should be the same default as in cad/surelog, cad/uhdm because surelog's lib is used in the yosys plugin cad/yosys-systemverilog
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SOLVERS_DESC= Install SAT solvers
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CVC5_DESC= CVC SAT Solver
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YICES_DESC= Yices SAT Solver
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Z3_DESC= Z3 SAT Solver
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CVC5_RUN_DEPENDS= cvc5:math/cvc5
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YICES_RUN_DEPENDS= yices_smt2:math/yices
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Z3_RUN_DEPENDS= z3:math/z3
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TCMALLOC_LDFLAGS= `pkg-config --libs libtcmalloc`
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TCMALLOC_LIB_DEPENDS= libtcmalloc.so:devel/google-perftools
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post-patch:
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${REINPLACE_CMD} -e '/^CXX =/d; s/^LD = .*/LD = $$(CXX)/' \
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-e '/^CONFIG/s/clang/${CHOSEN_COMPILER_TYPE}/' \
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${WRKSRC}/Makefile
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post-install:
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${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/yosys
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.include <bsd.port.mk>
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