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fb16dfecae
Commit b7f05445c0 has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner)
17 lines
980 B
Plaintext
17 lines
980 B
Plaintext
GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also
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implements some of the 2001 P1364 standard features including all three
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PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language
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Reference Manual (LRM).
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Verilog is the name for both a language for describing electronic hardware
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called a hardware description language (HDL) and the name of the program
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that simulates HDL circuit descriptions to verify that described circuits
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will function correctly when the are constructed. Verilog is used only for
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describing digital logic circuits. Other HDLs such as Spice are used for
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describing analog circuits. There is an IEEE standard named P1364 that
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standardizes the Verilog HDL and the behavior of Verilog simulators.
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Verilog is officially defined in the IEEE P1364 Language Reference
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Manual (LRM) that can be purchased from IEEE. There are many good books
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for learning that teach the Verilog HDL and/or that teach digital circuit
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design using Verilog.
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