mirror of
https://git.FreeBSD.org/ports.git
synced 2024-10-18 19:49:40 +00:00
5eee19a826
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. WWW: https://www.veripool.org/projects/verilator/wiki/Intro PR: 230761 Submitted by: Kevin Zheng <kevinz5000@gmail.com>
9 lines
485 B
Plaintext
9 lines
485 B
Plaintext
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
|
|
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
|
|
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
|
|
designed for large projects where fast simulation performance is of primary
|
|
concern, and is especially well suited to generate executable models of CPUs
|
|
for embedded software design teams.
|
|
|
|
WWW: https://www.veripool.org/projects/verilator/wiki/Intro
|