mirror of
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f71fa1b21a
Reported by: portscout
52 lines
1.7 KiB
Makefile
52 lines
1.7 KiB
Makefile
PORTNAME= cocotb
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DISTVERSIONPREFIX= v
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DISTVERSION= 1.9.1
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CATEGORIES= cad python
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PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX}
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MAINTAINER= yuri@FreeBSD.org
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COMMENT= Coroutine based cosimulation library for writing VHDL and Verilog
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WWW= https://www.cocotb.org/
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LICENSE= BSD3CLAUSE
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LICENSE_FILE= ${WRKSRC}/LICENSE
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BUILD_DEPENDS= ${PY_SETUPTOOLS} \
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${PYTHON_PKGNAMEPREFIX}wheel>0:devel/py-wheel@${PY_FLAVOR}
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RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}find-libpython>0:devel/py-find-libpython@${PY_FLAVOR} \
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gtkwave:cad/gtkwave
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TEST_DEPENDS= ${PYTHON_PKGNAMEPREFIX}pytest>0:devel/py-pytest@${PY_FLAVOR} \
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${PYTHON_PKGNAMEPREFIX}pytest-cov>0:devel/py-pytest-cov@${PY_FLAVOR} \
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${PYTHON_PKGNAMEPREFIX}pytest-mock>=3.10.0:devel/py-pytest-mock@${PY_FLAVOR}
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USES= python shebangfix
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USE_PYTHON= pep517 autoplist
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USE_GITHUB= yes
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SHEBANG_GLOB= *.py
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TEST_ENV= ${MAKE_ENV} PYTHONPATH=${STAGEDIR}${PYTHONPREFIX_SITELIBDIR} \
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PATH=${STAGEDIR}${LOCALBASE}/bin:${PATH} \
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LD_LIBRARY_PATH=${STAGEDIR}${PYTHONPREFIX_SITELIBDIR}/cocotb/libs \
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SIM=icarus
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OPTIONS_DEFINE= IVERILOG VERILATOR # GHDL - TODO
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OPTIONS_DEFAULT= IVERILOG VERILATOR
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IVERILOG_DESC= Iverilog dependency
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IVERILOG_RUN_DEPENDS= iverilog:cad/iverilog
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VERILATOR_DESC= Verilator dependency
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VERILATOR_RUN_DEPENDS= verilator:cad/verilator
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post-install:
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@${STRIP_CMD} \
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${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/simulator${PYTHON_EXT_SUFFIX}.so \
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${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/lib*.so \
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${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/libcocotbvpi_icarus.vpl
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do-test: # some tests fail, see https://github.com/cocotb/cocotb/issues/3236, https://github.com/cocotb/cocotb/issues/3435
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@cd ${TEST_WRKSRC} && ${SETENV} ${TEST_ENV} ${GMAKE} test
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.include <bsd.port.mk>
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