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31 lines
1.7 KiB
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31 lines
1.7 KiB
Plaintext
Chipmunk CAD (Jan 1993 Revision)
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-------- --- --- ---- --------
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This directory contains a revised public beta-test version of the
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Caltech electronic CAD distribution. This distribution contains tools
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for schematic capture, netlist creation, and analog and digital
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simulation (log), IC mask layout, extraction, and DRC (wol), simple
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chip compilation (wolcomp), MOSIS fabrication request generation
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(mosis), netlist comparison (netcmp), data plotting (view) and
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postscript graphics editing (until). These tools were used exclusively
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for the design and test of all the integrated circuits described in
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Carver Mead's book "Analog VLSI and Neural Systems". Until was used
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as the primary tool for figure creation for the book. The directory
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also contains an example of an analog VLSI chip that was designed and
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fabricated with these tools, and an example of an Actel
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field-programmable gate array design that was simulated and converted
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to Actel format with these tools (example).
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These tools were originally written for HP 200 Series ("Chipmunk")
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computers, and were later ported to Unix and the X Windows System.
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Many people contributed to the design and porting of these tools; we
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have made an attempt to credit authors in each package, and regret any
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omisions. Carver Mead provided the inspiration, initiative, and
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financial support for many of the tools in this package; in several
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cases (wol and wolcomp) he wrote the original prototypes as well. The
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Systems Development Foundation, Hewlett Packard, and the Office of
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Naval Research were the main sources of funding for these tools. These
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tools are distributed under a license very similar to the GNU license;
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the minor changes protect Caltech from liability. Each tar file
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contains this license.
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