mirror of
https://git.FreeBSD.org/ports.git
synced 2024-12-04 01:48:54 +00:00
10 lines
449 B
Plaintext
10 lines
449 B
Plaintext
Verilog-mode.el is a Verilog mode for Emacs which provides context-sensitive
|
|
highlighting, auto indenting, and provides macro expansion capabilities to
|
|
greatly reduce Verilog coding time.
|
|
|
|
Recent versions allow you to insert AUTOS in non-AUTO designs, so IP
|
|
interconnect can be easily modified. You can also expand Verilog-2001 ".*"
|
|
instantiations, to see what ports will be connected by simulators.
|
|
|
|
WWW: https://www.veripool.org/wiki/verilog-mode
|