mirror of
https://git.FreeBSD.org/ports.git
synced 2024-11-30 01:15:52 +00:00
5c50317594
PR: 208437 Submitted by: Matthias Petermann <matthias at petermann-it.de> (maintainer) |
||
---|---|---|
.. | ||
admesh | ||
adms | ||
alliance | ||
astk-client | ||
astk-serveur | ||
atlc | ||
basicdsp | ||
brickutils | ||
brlcad | ||
calculix | ||
cascade | ||
chipvault | ||
cider | ||
cura-engine | ||
dinotrace | ||
dxf2fig | ||
electric | ||
electric-ng | ||
elmerfem | ||
feappv | ||
fidocadj | ||
freehdl | ||
fritzing | ||
gdsreader | ||
gdt | ||
geda | ||
gerbv | ||
ghdl | ||
gmsh | ||
gmsh-occ | ||
gnucap | ||
gplcver | ||
gspiceui | ||
gtkwave | ||
impact | ||
irsim | ||
iverilog | ||
jspice3 | ||
kicad | ||
kicad-devel | ||
klayout | ||
layouteditor | ||
ldraw | ||
leocad | ||
librecad | ||
linux-eagle5 | ||
logisim | ||
magic | ||
meshdev | ||
meshlab | ||
netgen | ||
ngspice_rework | ||
opencascade | ||
openscad | ||
openvsp | ||
p5-GDS2 | ||
p5-Verilog-Perl | ||
pcb | ||
pdnmesh | ||
py-pycam | ||
pythoncad | ||
qcad | ||
qcad-partslib | ||
qelectrotech | ||
qfsm | ||
qmls | ||
qucs | ||
repsnapper | ||
sceptre | ||
scotch | ||
spice | ||
stepcode | ||
sweethome3d | ||
tkgate | ||
tochnog | ||
transcalc | ||
varkon | ||
verilog-mode.el | ||
xcircuit | ||
z88 | ||
Makefile |