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fb16dfecae
Commit b7f05445c0 has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner)
23 lines
1.3 KiB
Plaintext
23 lines
1.3 KiB
Plaintext
Features:
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* Visualization of signal states with measurement graphs.
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* Single gate mode to analyze oscillations.
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* Analysis and synthesis of combinatorial and sequential circuits.
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* Simple testing of circuits: You can create test cases and execute them to
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verify your design.
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* Includes a simple editor for finite state machines (FSM). A FSM can then be
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converted to a state transition table and a circuit implementing the FSM.
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* Contains a library with the most commonly used 74xx series integrated circuits
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* Supports generic circuits. This allows the creation of circuits that can be
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parameterized when used. In this way, it is possible, for e.g., to create a
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barrel shifter with a selectable bit width.
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* Supports large circuits: The "Conway's Game of Life" example consists of about
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2400 active components and works just fine.
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* It is possible to use custom components which are implemented in Java and
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packed in a jar file. See this example for details.
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* Simple remote TCP interface which e.g. allows an assembler IDE to control the
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simulator.
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* Components can be described using VHDL or Verilog. The open source VHDL
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simulator ghdl needs to be installed to simulate a VHDL defined component, and
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the open source Verilog simulator Icarus Verilog is required to simulate a
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Verilog defined component.
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