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fb16dfecae
Commit b7f05445c0 has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner)
18 lines
1.1 KiB
Plaintext
18 lines
1.1 KiB
Plaintext
The Verilog-Perl library is a building point for Verilog support in the Perl
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language. It includes:
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* Verilog::Getopt which parses command line options similar to C++ and VCS.
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* Verilog::Language which knows the language keywords and parses numbers.
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* Verilog::Netlist which builds netlists out of Verilog files. This allows
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easy scripts to determine things such as the hierarchy of modules.
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* Verilog::Parser invokes callbacks for language tokens.
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* Verilog::Preproc preprocesses the language, and allows reading
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post-processed files right from Perl without temporary files.
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* vpassert inserts PLIish warnings and assertions for any simulator.
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* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
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* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
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cross references and makes it easy to rename signal and module names across
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multiple files. Vrename uses a simple and efficient three step process.
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First, you run vrename to create a list of signals in the design. You then
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edit this list, changing as many symbols as you wish. Vrename is then run a
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second time to apply the changes.
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