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d4874a8dbb
- sparc: Fill in real SparcStation 10 values
- sparc: Fix co-processor branch and store ops (Aurelien Jarno)
- sparc: Fix stdfq op (Aurelien Jarno)
- mips: Clear BEV and ERL for the fake bootloader.
- 64bit MIPS FPUs have 32 registers.
- mips: Fix RDHWR handling. Code formatting. Don't use *_direct versions
to raise exceptions.
- mips: Fix disabling of the Cause register for R2.
- mips: Handle EBase properly.
- mips: Fix rotr immediate ops, mask shift/rotate arguments to their allowed
size.
- mips: fix branch delay slot cornercases.
- Fix for PowerPC 64 rotates.
- Fix for PowerPC 64 load & store with immediate index.
- SD card emulation (initial implementation by Andrzei Zaborowski).
- mips: Save state for all CP0 instructions, they may throw a CPU exception.
- mips: Fix handling of ADES exceptions.
- sparc: Enforce even float register pair for double register ops
(Aurelien Jarno)
- sparc: Full implementation of IEEE exceptions (Aurelien Jarno)
- mips: Fix ins/ext cornercase.
- mips: Actually skip over delay slot for a non-taken branch likely.
- mips: Set proper BadVAddress value for unaligned instruction fetch.
- mips: Implement prefx.
- PowerPC 64 fixes
- Unify IRQ handling.
- Fix TCX base on SS10
- Sparc32/64 CPU selection for user emulator
- Fix generated code disasm output on Sparc64 host
- ARM IRQ fix.
- mips: Remove bogus mtc0 handling.
- mips: Fix exception handling cornercase for rdhwr.
- mips: Catch unaligned sc/scd.
- mips: Mark watchpoint features as unimplemented.
- mips: Proper handling of reserved bits in the context register.
- mips: Fix CP0_IntCtl handling.
- Fix monitor disasm output for Sparc64 target
- Implement embedded IRQ controller for PowerPC 6xx/740 & 750.
Fix PowerPC external interrupt input handling and lowering.
Fix OpenPIC output pins management.
Fix multiples bugs in OpenPIC IRQ management.
Fix OpenPIC CPU(s) reset function.
Fix Mac99 machine to properly route OpenPIC outputs to the PowerPC
input pins.
Fix PREP machine to properly route i8259 output to the PowerPC external
interrupt pin.
- mips: More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may
end up empty for 32bit mips, which dyngen trips over.
- mips: Throw RI for invalid MFMC0-class instructions. Introduce optional
MIPS_STRICT_STANDARD define to adhere more to the spec than it makes
sense in normal operation.
- mips: Make SYNCI_Step and CCRes CPU-specific.
- Embedded PowerPC Device Control Registers infrastructure.
- Add PowerPC 405 input pins (IRQ, resets, ...) model.
- sparc: Alignment check mechanism (not fully enabled yet) (Aurelien Jarno)
- Fix Sparc64 wrfprs, move VIS ops where they belong, more VIS ops
- Fix Sparc32 device save methods
- mips: Another fix for CP0 Cause register handling.
- Add TARGET_FMT_plx to properly display target_phys_addr_t variables.
- Fix miscellaneous display warnings for PowerPC & alpha targets
and parallel CFI flash driver.
- Know about more PCI device classes.
- mips: Restart interrupts after an exception.
- Add device save and reset methods to FDC and M48T59
- Fix Sparc64 double float gdb protocol (initial version by Paul Brook)
- gdbstub: Fix format specified for watchpoint address.
- Update OpenBIOS for Sparc32 and add a Sparc64 image
- Gallileo fixes, by Stefan Weil.
- mips: Small code generation optimization.
- mips: Fix qemu SIGFPE caused by division-by-zero due to underflow.
- mips: Don't use T2 for INS, it conflicts with branch delay slot handling.
- mips: Simplify branch likely handling.
- Fix a lot of debug traces for PowerPC emulation: use logfile instead of
stdout
- Parallel flash bugfixes:
- always need to register flash area back to IO_MEM_ROMD at reset time
- disabled buffered write as it's not actually supported
- don't check flash time at registration time
- PowerPC emulation bugfixes:
- don't generate multiple exit_tb at the end of conditional branches
- disable TRACE exception as it is not correct for embedded PowerPC.
- Add bus model (or input pins) into PowerPC CPU flags.
Add PowerPC 970 bus and exceptions model.
Add code provision for PowerPC 970 instanciation.
- PREP and heathrow machines only support PowerPC CPU with a 6xx bus.
Mac99 machine may also support PowerPC 970 CPU.
- Add reset callbacks for PowerPC CPU.
Move cpu_ppc_init, cpu_ppc_close, cpu_ppc_reset and ppc_tlb_invalidate
into helper.c as they are to be called from outside of the translated code.
- PowerPC 4xx software driven TLB fixes + debug traces.
Add code provision for more MMU models support.
- Cleanup and add more PowerPC core definitions.
- Memory-mapped interface for PS/2 controller, by Herve Poussineau.
- Memory-mapped interface for RTC, by Herve Poussineau.
- Acer Pica 61 machine, by Herve Poussineau.
- Update OpenBIOS Sparc images to SVN 125
- Add callbacks to allow dynamic change of PowerPC clocks (to be improved)
Fix embedded PowerPC watchdog and timers
Fix PowerPC 405 SPR
Add generic PowerPC 405 core instanciation code + resets support.
Implement simple peripherals shared by most PowerPC 405 implementations
PowerPC 405 EC & EP microcontrollers preliminary support
- Support it_shift for mmapped pckbd.
- Move PowerPC 405 specific definitions into a separate file
Preliminary code for -kernel option support for PowerPC 405 boards
Fix DBSR in case of PowerPC 405 chip reset
Add enums for PowerPC 405 clocks.
Fix IRQ numbers (IBM reversed bits numbering...)
Fix SPRG4-7 read access right
Fix MSR mask in CPU definitions
- mips: Choose number of TLBs at runtime, by Herve Poussineau.
- Fix mmapped register alignment and endianness handling.
- TCX palette bug fix
- Ptable calculation broken for 32bit code under x86_64, by Bernhard Kauer.
- Another lsi53c895a patch, by Wang Cheng Yeh.
- Fix keyboard detection bugs
- Duplicated SPR fix for BookE PowerPC by Guglielmo Morandin
- More Gallileo register initialization, by Aurelien Jarno and Stefan Weil.
- Fix keyboard serial and mouse bugs
- TCX 24 bit model support
- lsi53c895a: Typo fix, by Wang Cheng Yeh.
- Sparc64 update: more VIS ops
- PowerPC embedded timers fixes.
Improve PowerPC timers debug.
- PowerPC 405 microcontrollers fixes and improvments:
- use target_phys_addr_t for physical addresses / offsets
- implement fake general purpose timers and memory access layer
for PowerPC 405EP
- more assigned internal IRQs.
- Improve PowerPC 405 MMU model / share more code for other embedded targets
support.
Fix PowerPC 405 MSR mask.
- Code provision for new PowerPC embedded target support with:
- 1 kB page size
- 64 bits GPR
- 64 bits physical address space
- SPE extension support.
Change TARGET_PPCSPE into TARGET_PPCEMB
- Add -pflash option to register parallel flash bloc devices.
- New target for embedded PowerPC emulation (only system emulation, for now).
- Evaluation boards for PowerPC 405EP.
- mips malta: Improved mini-bootloader, based on a patch by Alec Voropay.
- mips: Fix lui sign extension.
- Update Sparc32 rom to support *BSD boot and 24 bit TCX
- i386: Workaround qemu guest SIGSEGVs with cmpxchg8b insn, by Juergen Keil.
- Fix Sparc32 ldscript
- lsi53c895a: Fix length mismatch condition, by Wang Cheng Yeh.
- scsi-disk: Buffer length fixes, by Wang Cheng Yeh.
- mips: Switch default CPU to 24Kf for now, as the Linux FPU emulation in
the current qemu mips emulation fails in some cases. (The Linux
FPU emulation works on real FPU-less hardware.)
- Memory-mapped interface for VGA, by Herve Poussineau.
- Crop VNC update requests to avoid segfaults, by Thomas Tuttle.
- Fix ARM fine pagetables.
- sparc: Fix CPU type zapped by system_reset
- More Sparc32 CPUs
- mips: Kill broken host register definitions, thanks to Paul Brook and Herve
Poussineau for debugging this.
- PCMCIA bus support. Parts of CF-ATA command set. Hitachi DSCM microdrive emulation.
- Core features of ARM XScale processors. Main PXA270 and PXA255 peripherals.
- Remove repeated code and enable encrypted SD cards and USB sticks images.
- Add remaining PXA2xx on-chip peripherals except I2C master.
- Implement iwMMXt instruction set for the PXA270 cpu.
- NAND Flash memory emulation and ECC calculation helpers for use by
NAND controllers.
- Texas Instruments ADS7846 ADC chip.
- Maxim MAX1110/1111 ADC chip.
- Spitz PDA, example PXA270 machine (four similar models).
- Account for machine with RAM which is not mapped at 0x0 in arm_boot.c.
- PL050 status register fixes.
- Honour limited subset of --cpu values instead of ignoring.
- Implement power state changes (IDLE and SLEEP) for PXA.
- -show-cursor switch to inhibit SDL hiding cursor.
- Set OpenBIOS variables in NVRAM
- Don't define HIGH_LATENCY for ARM, this was a workaround for an ALSA problem.
- Handle division by zero case in Sparc64 udivx and sdivx ops
- vmwarevga: Change the PCI IO region start to that hardcoded in VBE bios
(reported by Jeremy Katz)
- mips: Support for simple YAMON output, by Alec Voropay.
- Some bits of Linux/MIPS host support, still segfaulty.
- mips: Fix a really stupid bug in the [ls]d[lr] emulation, by Herve Poussineau.
- sparc: Fix slavio_misc base
- Add dummy THC and TEC registers to TCX
- mips: Clear BD slot on next exception if appropriate.
- MIPS 64-bit FPU support, plus some collateral bugfixes in the
conditional branch handling.
- sparc: Fix pc/npc for unaligned load/stores, maybe other exceptions
- Update OpenBIOS/Sparc32 to SVN 144. Changes:
- Fix power-management location
- Fix out of bounds accesses
- Increase virtual memory supply to meet NetBSD and OpenBSD demand
- More obviously alarming return values for find_pte
- Fix unaligned memory access
- Fix memory corruption problems reported by glibc
- Fix boot-device use
- Use nvram boot-args and boot-device variables
- Set variable defaults before nvram_init
- Improve escape sequence handling
- Fix nvram parameter area
- More Sparc32 CPUs
- Clear preloaded kernel parameters to avoid crash at reset
- sparc: Enable unaligned access faults
- ARM946 CPU support.
- Switch to qemu_ram_alloc() for memory allocation in PXA255/270.
Pass correct RAM size to arm_load_kernel (currently unused) - thanks to
BobOfDoom.
Register the Xscale Internal Memory Storage.
- pxa: Set OOK when OON is set in OSCC register (thanks to BobOfDoom).
Correct a fatal typo in timer code.
- Correct the number of PXA255 GPIO lines. Reuse the PXA timers struct for
PXA27x additional timers.
- Fix MIPS64 address computation specialcase, by Aurelien Jarno.
- Preliminary MIPS 64-bit MMU implementation, by Aurelien Jarno.
- PCMCIA addresses are 26-bit, widen the address type from 16 to 32 bits.
- Fix wrong branch condition in MIPS testandset.
- mips: Fix for the scd instruction, by Aurelien Jarno.
- mips: Fix missing status ro mask initialization, thanks Stefan Weil.
- Improved debug output for the MIPS opcode decoder.
- mips: Implement FP madd/msub, wire up bc1any[24][ft].
- mips: Implemented cabs FP instructions, and improve exception handling for
trunc/floor/ceil/round.
- Fix softfloat NaN handling.
- Correct NAND erase block size. Misc fixes in Spitz code.
- Allow VMware-SVGA operation enable before command FIFO is configured.
Implement "screendump" for 32 bit colour depth.
- MIPS TLB style selection at runtime, by Herve Poussineau.
- mips: MMU code improvements, by Aurelien Jarno.
- Don't decode CP0 XContext on 32bit MIPS.
- Add fpu register support to the gdb code, by Magnus Damm.
- Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno.
- Full MIPS64 MMU implementation, by Aurelien Jarno.
- More generic 64 bit multiplication support, by Aurelien Jarno.
- sparc: Force the primary CPU to run and other CPUs to halt, recalculate
timers after system_reset.
- sparc: Set limits for memory size to avoid overlap with devices
- Enable faults for unassigned memory accesses and unimplemented ASIs
- Fix Qemu division by zero triggered by NetBSD
- Make TCX registers match what NetBSD expects
- mips: Work around the lack of proper handling for self-modifying code.
- mips: Move FPU exception handling into helper functions, since they are big.
- Fix FP-conditional branches.
- Check FPU register mode at runtime, not translation time, as the F64
status bit can change.
- Fix sysrq support from the monitor mux (originally by Jason Wessel).
- Use full 36-bit physical address space on SS10
- Update Sparc32 OpenBIOS image to SVN revision 149. Changes:
r145: Fix power-management location for SS-10
r146: Fix overallocation
r147: NetBSD and OpenBSD fixes:
- Correct timer and interrupt controller mappings
- Add ESP clock frequency to avoid division by zero
- CS4231 exists only in SS5
- Disable BPP for now, it's not emulated by Qemu anyway
With these fixes, one NetBSD kernel even got to root device prompt on SS5.
r148: Update vsprintf.c from Linux to get 64-bit output
r149: Use full 36-bit physical address space on SS10
- mips: Fix ldl/ldr implementation, by Aurelien Jarno.
- Fix slti/sltiu for MIPS64, by Aurelien Jarno.
- More MIPS 64-bit FPU support.
- Linux loader rewrite, by H. Peter Anvin.
- mips: Fix indexed FP load/store instructions.
- mips: Catch more MIPS FPU cornercases, fix addr.ps and mulr.ps instructions.
- M68k addx/subx fix.
- arm: Don't touch carry flag in ASR <reg> with zero <reg>, submitted by
Aurelien Jarno.
- Fix interrupt controller address masking
- I2C/SMBus framework.
- mips: The previous patch to make breakpoints work was a performance
disaster, use a similiar hack as ARM does instead.
- mips: The 24k wants more watch and srsmap registers.
- m68k/ColdFire system emulation.
- Implement the PXA2xx I2C master controller.
Fix PXA270-specific timers and make minor changes in other PXA parts.
- Add WM8750 and MAX7310 chips (I2C slaves).
Wolfson Microsystems WM8750 audio chip and Maxim MAX7310 gpio expander
chip are used in the Spitz.
- Speed up m68k by 20%.
- Use i2c_slave_init() to allocate the PXA (dummy) I2C slave.
Hush the warning:
hw/pc.c:402: warning: control reaches end of non-void function
- Savevm/loadvm bits for ARM core, the PXA2xx peripherals and Spitz hardware.
- Commit NAND image changes on "commit all" or "commit mtd".
- Change ptimer API to use 64-bit values, add save and load methods
Use ptimers for Sparc32 Slavio
- Implement Sparc64 CPU timers using ptimers
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