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mirror of https://git.FreeBSD.org/ports.git synced 2025-01-15 07:56:36 +00:00
freebsd-ports/cad
2021-12-29 17:07:55 -05:00
..
abc
admesh
adms
alliance framework: Add new USES 'magick' for graphics/ImageMagick* 2021-12-11 14:50:53 +01:00
appcsxcad
archimedes
astk-client
astk-serveur
atlc
basicdsp
brlcad
calculix
calculix-ccx
caneda
cascade
cascade-compiler
chipvault
csxcad
cura
cura-engine
cvc cad/cvc: New port: Circuit Validity Checker 2021-12-28 23:37:20 -08:00
digital
dinotrace
ecpprog
electric
electric-ng
fasm
fdm_materials
feappv
fidocadj
freecad
freehdl
fritzing
gds3d
gdsreader
gdt
geda
gerbv
ghdl
gmsh cad/gmsh: Update to 4.9.2 2021-12-26 12:10:15 +08:00
gnucap
gplcver
graywolf
gspiceui
gtkwave
horizon-eda */*: bump ports depending on libgit2 2021-12-04 13:07:30 +01:00
ifcopenshell
impact
irsim
iverilog
jspice3
k40-whisperer
kicad
kicad-devel cad/kicad-devel: Update 2021-12-20 18:44:56 +01:00
kicad-doc
kicad-library-footprints
kicad-library-footprints-devel cad/kicad-devel: Update kicad-*-devel 2021-12-20 18:56:01 +01:00
kicad-library-packages3d
kicad-library-packages3d-devel cad/kicad-devel: Update kicad-*-devel 2021-12-20 18:56:01 +01:00
kicad-library-symbols
kicad-library-symbols-devel cad/kicad-devel: Update kicad-*-devel 2021-12-20 18:56:01 +01:00
kicad-library-templates
kicad-library-templates-devel cad/kicad-devel: Update kicad-*-devel 2021-12-20 18:56:01 +01:00
klayout cad/klayout: Unbreak build 2021-12-25 23:05:50 -08:00
ktechlab
ldraw
ldview
leocad
lepton-eda cad/lepton-eda: Update to 1.9.17 2021-12-29 17:07:55 -05:00
libopencad
librecad
libredwg
librepcb
linux-eagle5
logisim
magic cad/magic: Maintainer reset, take maintainership 2021-12-28 10:17:28 -08:00
meshdev
meshlab
NASTRAN-95
netgen cad/netgen: don't set -march=native 2021-12-23 22:18:10 +00:00
netgen-lvs cad/netgen-lvs: Update 1.5.210 -> 1.5.211 2021-12-22 18:56:24 -08:00
ngspice_rework
nvc
opencascade
openctm
openfpgaloader cad/openfpgaloader: Update 0.5.0 -> 0.6.1 2021-12-11 00:41:22 -08:00
openroad
openscad
openscad-devel
opentimer
openvsp
oregano
p5-GDS2
p5-Verilog-Perl cad/p5-Verilog-Perl: update to 3.478 2021-12-23 19:33:28 +09:00
pcb
pdnmesh
PrusaSlicer
py-cadquery
py-cq-editor
py-ezdxf
py-gdspy
py-lcapy
py-ocp
py-phidl
py-pyfda
py-pymtl cad/py-pymtl: New port: Python-based hardware generation, simulation, verification framework 2021-12-26 18:31:33 -08:00
python-gdsii
qcad
qcsxcad
qelectrotech
qflow
qmls
qrouter
repsnapper
rubygem-gdsii
scotch
solvespace
sp2sp
spice
stepcode
stm32flash
sumo
surelog cad/surelog: New port: SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc 2021-12-27 09:09:30 -08:00
sweethome3d cad/sweethome3d: update Sweet Home 3D to version 6.6.4. 2021-12-13 13:17:30 +00:00
tkgate
tochnog
uhdm cad/uhdm: New port: Universal Hardware Data Model 2021-12-27 09:29:43 -08:00
uranium
verilator cad/verilator: Update 4.214 -> 4.216 2021-12-12 13:52:38 -08:00
verilog-mode.el
veroroute
xcircuit
yosys
z88
zcad
Makefile cad/cvc: New port: Circuit Validity Checker 2021-12-28 23:37:20 -08:00