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a20392af84
language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
92 lines
1.9 KiB
Makefile
92 lines
1.9 KiB
Makefile
# $FreeBSD$
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#
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COMMENT = CAD tools
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SUBDIR += admesh
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SUBDIR += adms
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SUBDIR += alliance
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SUBDIR += astk-client
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SUBDIR += astk-serveur
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SUBDIR += atlc
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SUBDIR += basicdsp
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SUBDIR += brlcad
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SUBDIR += calculix
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SUBDIR += cascade
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SUBDIR += chipmunk
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SUBDIR += chipvault
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SUBDIR += cider
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SUBDIR += dinotrace
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SUBDIR += dxf2fig
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SUBDIR += electric
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SUBDIR += electric-ng
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SUBDIR += fandango
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SUBDIR += feappv
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SUBDIR += findhier
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SUBDIR += freecad
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SUBDIR += freehdl
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SUBDIR += gdsreader
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SUBDIR += gdt
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SUBDIR += geda
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SUBDIR += geda-docs
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SUBDIR += geda-examples
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SUBDIR += geda-gattrib
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SUBDIR += geda-gschem
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SUBDIR += geda-netlist
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SUBDIR += geda-symbols
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SUBDIR += geda-symcheck
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SUBDIR += geda-utils
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SUBDIR += gerbv
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SUBDIR += gmsh
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SUBDIR += gmsh-occ
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SUBDIR += gnucap
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SUBDIR += gplcver
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SUBDIR += gspiceui
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SUBDIR += gtkwave
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SUBDIR += gtkwave3
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SUBDIR += gwave
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SUBDIR += impact
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SUBDIR += irsim
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SUBDIR += iverilog
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SUBDIR += jspice3
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SUBDIR += kicad
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SUBDIR += klayout
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SUBDIR += leocad
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SUBDIR += libgeda
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SUBDIR += linux-eagle
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SUBDIR += linux-gid
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SUBDIR += magic
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SUBDIR += mars
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SUBDIR += netgen
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SUBDIR += ngspice_rework
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SUBDIR += opencascade
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SUBDIR += opencascade-tutorial
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SUBDIR += oregano
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SUBDIR += p5-GDS2
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SUBDIR += p5-Verilog-Perl
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SUBDIR += pcb
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SUBDIR += pdnmesh
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SUBDIR += pythoncad
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SUBDIR += qcad
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SUBDIR += qcad-partslib
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SUBDIR += qfsm
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SUBDIR += qmls
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SUBDIR += qucs
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SUBDIR += sceptre
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SUBDIR += scotch
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SUBDIR += scv
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SUBDIR += slffea
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SUBDIR += spice
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SUBDIR += systemc
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SUBDIR += tclspice
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SUBDIR += tkgate
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SUBDIR += tochnog
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SUBDIR += transcalc
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SUBDIR += varkon
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SUBDIR += verilog-mode.el
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SUBDIR += vipec
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SUBDIR += xcircuit
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SUBDIR += z88
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.include <bsd.port.subdir.mk>
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