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30 lines
683 B
Makefile
30 lines
683 B
Makefile
# $FreeBSD$
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PORTNAME= verilator
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DISTVERSION= 4.020
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CATEGORIES= cad
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MASTER_SITES= https://www.veripool.org/ftp/
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MAINTAINER= kevinz5000@gmail.com
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COMMENT= Synthesizable Verilog to C++ compiler
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LICENSE= GPLv3
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LICENSE_FILE= ${WRKSRC}/LICENSE
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USES= bison compiler:c++14-lang gmake pathfix perl5 tar:tgz
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GNU_CONFIGURE= yes
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CONFIGURE_ENV= INSTALL_PROGRAM="${INSTALL_SCRIPT}"
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post-patch:
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${REINPLACE_CMD} -e 's|@pkgconfigdir@|${PREFIX}/libdata/pkgconfig|' \
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${WRKSRC}/Makefile.in
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post-build:
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@${STRIP_CMD} ${WRKSRC}/bin/verilator_bin
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post-install:
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@${RM} ${STAGEDIR}${PREFIX}/bin/verilator_bin_dbg ${STAGEDIR}${PREFIX}/bin/verilator_coverage_bin_dbg
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.include <bsd.port.mk>
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