mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-21 11:13:30 +00:00
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
|
/*
|
||
|
* Instruction formats for the sequencer program downloaded to
|
||
|
* Aic7xxx SCSI host adapters
|
||
|
*
|
||
|
* Copyright (c) 1997 Justin T. Gibbs.
|
||
|
* All rights reserved.
|
||
|
*
|
||
|
* Redistribution and use in source and binary forms, with or without
|
||
|
* modification, are permitted provided that the following conditions
|
||
|
* are met:
|
||
|
* 1. Redistributions of source code must retain the above copyright
|
||
|
* notice immediately at the beginning of the file, without modification,
|
||
|
* this list of conditions, and the following disclaimer.
|
||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||
|
* notice, this list of conditions and the following disclaimer in the
|
||
|
* documentation and/or other materials provided with the distribution.
|
||
|
* 3. The name of the author may not be used to endorse or promote products
|
||
|
* derived from this software without specific prior written permission.
|
||
|
*
|
||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
|
||
|
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||
|
* SUCH DAMAGE.
|
||
|
*
|
||
|
* $Id$
|
||
|
*/
|
||
|
|
||
|
struct ins_format1 {
|
||
|
u_int8_t immediate;
|
||
|
u_int8_t source;
|
||
|
u_int8_t destination;
|
||
|
u_int8_t opcode_ret;
|
||
|
};
|
||
|
|
||
|
struct ins_format2 {
|
||
|
u_int8_t shift_control;
|
||
|
u_int8_t source;
|
||
|
u_int8_t destination;
|
||
|
u_int8_t opcode_ret;
|
||
|
#define RETURN_BIT 0x01
|
||
|
};
|
||
|
|
||
|
struct ins_format3 {
|
||
|
u_int8_t immediate;
|
||
|
u_int8_t source;
|
||
|
u_int8_t address;
|
||
|
u_int8_t opcode_addr;
|
||
|
#define ADDR_HIGH_BIT 0x01
|
||
|
};
|
||
|
|
||
|
struct instruction {
|
||
|
union {
|
||
|
struct ins_format1 format1;
|
||
|
struct ins_format2 format2;
|
||
|
struct ins_format3 format3;
|
||
|
u_int8_t bytes[4];
|
||
|
} format;
|
||
|
u_int srcline;
|
||
|
struct symbol *patch_label;
|
||
|
STAILQ_ENTRY(instruction) links;
|
||
|
};
|
||
|
|
||
|
#define AIC_OP_OR 0x0
|
||
|
#define AIC_OP_AND 0x1
|
||
|
#define AIC_OP_XOR 0x2
|
||
|
#define AIC_OP_ADD 0x3
|
||
|
#define AIC_OP_ADC 0x4
|
||
|
#define AIC_OP_ROL 0x5
|
||
|
|
||
|
#define AIC_OP_JMP 0x8
|
||
|
#define AIC_OP_JC 0x9
|
||
|
#define AIC_OP_JNC 0xa
|
||
|
#define AIC_OP_CALL 0xb
|
||
|
#define AIC_OP_JNE 0xc
|
||
|
#define AIC_OP_JNZ 0xd
|
||
|
#define AIC_OP_JE 0xe
|
||
|
#define AIC_OP_JZ 0xf
|
||
|
|
||
|
/* Pseudo Ops */
|
||
|
#define AIC_OP_SHL 0x10
|
||
|
#define AIC_OP_SHR 0x20
|
||
|
#define AIC_OP_ROR 0x30
|