1998-09-15 07:25:33 +00:00
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/*
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2000-09-16 20:02:28 +00:00
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* FreeBSD, PCI product support functions
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1998-09-15 07:25:33 +00:00
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*
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2001-01-27 20:54:24 +00:00
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* Copyright (c) 1995-2001 Justin T. Gibbs
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1998-09-15 07:25:33 +00:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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2000-07-18 20:12:14 +00:00
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* Alternatively, this software may be distributed under the terms of the
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* GNU Public License ("GPL").
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1998-09-15 07:25:33 +00:00
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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2002-12-31 04:22:36 +00:00
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* $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/ahc_pci.c#12 $
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2000-09-16 20:02:28 +00:00
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*
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1999-08-28 01:08:13 +00:00
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* $FreeBSD$
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1998-09-15 07:25:33 +00:00
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*/
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2002-04-24 16:58:51 +00:00
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#include <dev/aic7xxx/aic7xxx_osm.h>
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1999-05-14 05:09:24 +00:00
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2000-09-16 20:02:28 +00:00
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#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */
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#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
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1998-09-15 07:25:33 +00:00
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1999-04-23 23:30:22 +00:00
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static int ahc_pci_probe(device_t dev);
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static int ahc_pci_attach(device_t dev);
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1998-09-15 07:25:33 +00:00
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2002-04-24 16:58:51 +00:00
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static device_method_t ahc_pci_device_methods[] = {
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1999-04-23 23:30:22 +00:00
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/* Device interface */
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DEVMETHOD(device_probe, ahc_pci_probe),
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DEVMETHOD(device_attach, ahc_pci_attach),
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ahc_eisa.c:
ahc_pci.c:
Add detach support.
Make use of soft allocated on our behalf by newbus.
For PCI devices, disable the mapping type we aren't
using for extra protection from rogue code.
aic7xxx_93cx6.c:
aic7xxx_93cx6.h:
Sync perforce IDs.
aic7xxx_freebsd.c:
Capture the eventhandle returned by EVENTHANDER_REGISTER
so we can kill the handler off during detach.
Use AHC_* constants instead of hard coded numbers in a
few more places.
Test PPR option state when deciding to "really" negotiate
when the CAM_NEGOTIATE flag is passed in a CCB.
Make use of core "ahc_pause_and_flushwork" routine in our
timeout handler rather than re-inventing this code.
Cleanup all of our resources (really!) in ahc_platform_free().
We should be all set to become a module now.
Implement the core ahc_detach() routine shared by all of
the FreeBSD front-ends.
aic7xxx_freebsd.h:
Softc storage for our event handler.
Null implementation for the ahc_platform_flushwork() OSM
callback. FreeBSD doesn't need this as XPT callbacks are
safe from all contexts and are done directly in ahc_done().
aic7xxx_inline.h:
Implement new lazy interrupt scheme. To avoid an extra
PCI bus read, we first check our completion queues to
see if any work has completed. If work is available, we
assume that this is the source of the interrupt and skip
reading INTSTAT. Any remaining interrupt status will be
cleared by a second call to the interrupt handler should
the interrupt line still be asserted. This drops the
interrupt handler down to a single PCI bus read in the
common case of I/O completion. This is the same overhead
as in the not so distant past, but the extra sanity of
perforning a PCI read after clearing the command complete
interrupt and before running the completion queue to avoid
missing command complete interrupts added a cycle.
aic7xxx.c:
During initialization, be sure to initialize all scratch
ram locations before they are read to avoid parity errors.
In this case, we use a new function, ahc_unbusy_tcl() to
initialize the scratch ram busy target table.
Replace instances of ahc_index_busy_tcl() used to unbusy
a tcl without looking at the old value with ahc_unbusy_tcl().
Modify ahc_sent_msg so that it can find single byte messages.
ahc_sent_msg is now used to determine if a transfer negotiation
attempt resulted in a bus free.
Be more careful in filtering out only the SCSI interrupts
of interest in ahc_handle_scsiint.
Rearrange interrupt clearing code to ensure that at least
one PCI transaction occurrs after hitting CLRSINT1 and
writting to CLRINT. CLRSINT1 writes take a bit to
take effect, and the re-arrangement provides sufficient
delay to ensure the write to CLRINT is effective. The
old code might report a spurious interrupt on some "fast"
chipsets.
export ahc-update_target_msg_request for use by OSM code.
If a target does not respond to our ATN request, clear
it once we move to a non-message phase. This avoids
sending a MSG_NOOP in some later message out phase.
Use max lun and max target constants instead of
hard-coded values.
Use softc storage built into our device_t under FreeBSD.
Fix a bug in ahc_free() that caused us to delete
resources that were not allocated.
Clean up any tstate/lstate info in ahc_free().
Clear the powerdown state in ahc_reset() so that
registers can be accessed.
Add a preliminary function for pausing the chip and
processing any posted work.
Add a preliminary suspend and resume functions.
aic7xxx.h:
Limit the number of supported luns to 64. We don't
support information unit transfers, so this is the
maximum that makes sense for these chips.
Add a new flag AHC_ALL_INTERRUPTS that forces the
processing of all interrupt state in a single invokation
of ahc_intr(). When the flag is not set, we use the
lazy interrupt handling scheme.
Add data structures to store controller state while
we are suspended.
Use constants instead of hard coded values where appropriate.
Correct some harmless "unsigned/signed" conflicts.
aic7xxx.seq:
Only perform the SCSIBUSL fix on ULTRA2 or newer controllers.
Older controllers seem to be confused by this.
In target mode, ignore PHASEMIS during data phases.
This bit seems to be flakey on U160 controllers acting
in target mode.
aic7xxx_pci.c:
Add support for the 29160C CPCI adapter.
Add definitions for subvendor ID information
available for devices with the "9005" vendor id.
We currently use this information to determine
if a multi-function device doesn't have the second
channel hooked up on a board.
Add rudimentary power mode code so we can put the
controller into the D0 state. In the future this
will be an OSM callback so that in FreeBSD we don't
duplicate functionality provided by the PCI code.
The powerstate code was added after I'd completed
my regression tests on this code.
Only capture "left over BIOS state" if the POWRDN
setting is not set in HCNTRL.
In target mode, don't bother sending incremental
CRC data.
2000-12-20 01:11:37 +00:00
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DEVMETHOD(device_detach, ahc_detach),
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1999-04-23 23:30:22 +00:00
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{ 0, 0 }
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};
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static driver_t ahc_pci_driver = {
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2002-09-22 23:03:31 +00:00
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"ahc",
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2002-04-24 16:58:51 +00:00
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ahc_pci_device_methods,
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1999-04-23 23:30:22 +00:00
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sizeof(struct ahc_softc)
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1998-09-15 07:25:33 +00:00
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};
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2002-09-22 23:03:31 +00:00
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DRIVER_MODULE(ahc_pci, pci, ahc_pci_driver, ahc_devclass, 0, 0);
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DRIVER_MODULE(ahc_pci, cardbus, ahc_pci_driver, ahc_devclass, 0, 0);
|
2001-05-15 19:41:12 +00:00
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MODULE_DEPEND(ahc_pci, ahc, 1, 1, 1);
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MODULE_VERSION(ahc_pci, 1);
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1998-09-15 07:25:33 +00:00
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1999-05-17 21:53:09 +00:00
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static int
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ahc_pci_probe(device_t dev)
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{
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2000-09-16 20:02:28 +00:00
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struct ahc_pci_identity *entry;
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1999-05-17 21:53:09 +00:00
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entry = ahc_find_pci_device(dev);
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if (entry != NULL) {
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device_set_desc(dev, entry->name);
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return (0);
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1999-04-23 23:30:22 +00:00
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}
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return (ENXIO);
|
1998-09-15 07:25:33 +00:00
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}
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1999-04-23 23:30:22 +00:00
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static int
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ahc_pci_attach(device_t dev)
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1998-09-15 07:25:33 +00:00
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{
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2000-09-16 20:02:28 +00:00
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struct ahc_pci_identity *entry;
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struct ahc_softc *ahc;
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char *name;
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int error;
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1999-04-23 23:30:22 +00:00
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1999-05-17 21:53:09 +00:00
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entry = ahc_find_pci_device(dev);
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if (entry == NULL)
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return (ENXIO);
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1998-09-15 07:25:33 +00:00
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2000-09-16 20:02:28 +00:00
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/*
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* Allocate a softc for this card and
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* set it up for attachment by our
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* common detect routine.
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*/
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name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT);
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if (name == NULL)
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return (ENOMEM);
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strcpy(name, device_get_nameunit(dev));
|
ahc_eisa.c:
ahc_pci.c:
Add detach support.
Make use of soft allocated on our behalf by newbus.
For PCI devices, disable the mapping type we aren't
using for extra protection from rogue code.
aic7xxx_93cx6.c:
aic7xxx_93cx6.h:
Sync perforce IDs.
aic7xxx_freebsd.c:
Capture the eventhandle returned by EVENTHANDER_REGISTER
so we can kill the handler off during detach.
Use AHC_* constants instead of hard coded numbers in a
few more places.
Test PPR option state when deciding to "really" negotiate
when the CAM_NEGOTIATE flag is passed in a CCB.
Make use of core "ahc_pause_and_flushwork" routine in our
timeout handler rather than re-inventing this code.
Cleanup all of our resources (really!) in ahc_platform_free().
We should be all set to become a module now.
Implement the core ahc_detach() routine shared by all of
the FreeBSD front-ends.
aic7xxx_freebsd.h:
Softc storage for our event handler.
Null implementation for the ahc_platform_flushwork() OSM
callback. FreeBSD doesn't need this as XPT callbacks are
safe from all contexts and are done directly in ahc_done().
aic7xxx_inline.h:
Implement new lazy interrupt scheme. To avoid an extra
PCI bus read, we first check our completion queues to
see if any work has completed. If work is available, we
assume that this is the source of the interrupt and skip
reading INTSTAT. Any remaining interrupt status will be
cleared by a second call to the interrupt handler should
the interrupt line still be asserted. This drops the
interrupt handler down to a single PCI bus read in the
common case of I/O completion. This is the same overhead
as in the not so distant past, but the extra sanity of
perforning a PCI read after clearing the command complete
interrupt and before running the completion queue to avoid
missing command complete interrupts added a cycle.
aic7xxx.c:
During initialization, be sure to initialize all scratch
ram locations before they are read to avoid parity errors.
In this case, we use a new function, ahc_unbusy_tcl() to
initialize the scratch ram busy target table.
Replace instances of ahc_index_busy_tcl() used to unbusy
a tcl without looking at the old value with ahc_unbusy_tcl().
Modify ahc_sent_msg so that it can find single byte messages.
ahc_sent_msg is now used to determine if a transfer negotiation
attempt resulted in a bus free.
Be more careful in filtering out only the SCSI interrupts
of interest in ahc_handle_scsiint.
Rearrange interrupt clearing code to ensure that at least
one PCI transaction occurrs after hitting CLRSINT1 and
writting to CLRINT. CLRSINT1 writes take a bit to
take effect, and the re-arrangement provides sufficient
delay to ensure the write to CLRINT is effective. The
old code might report a spurious interrupt on some "fast"
chipsets.
export ahc-update_target_msg_request for use by OSM code.
If a target does not respond to our ATN request, clear
it once we move to a non-message phase. This avoids
sending a MSG_NOOP in some later message out phase.
Use max lun and max target constants instead of
hard-coded values.
Use softc storage built into our device_t under FreeBSD.
Fix a bug in ahc_free() that caused us to delete
resources that were not allocated.
Clean up any tstate/lstate info in ahc_free().
Clear the powerdown state in ahc_reset() so that
registers can be accessed.
Add a preliminary function for pausing the chip and
processing any posted work.
Add a preliminary suspend and resume functions.
aic7xxx.h:
Limit the number of supported luns to 64. We don't
support information unit transfers, so this is the
maximum that makes sense for these chips.
Add a new flag AHC_ALL_INTERRUPTS that forces the
processing of all interrupt state in a single invokation
of ahc_intr(). When the flag is not set, we use the
lazy interrupt handling scheme.
Add data structures to store controller state while
we are suspended.
Use constants instead of hard coded values where appropriate.
Correct some harmless "unsigned/signed" conflicts.
aic7xxx.seq:
Only perform the SCSIBUSL fix on ULTRA2 or newer controllers.
Older controllers seem to be confused by this.
In target mode, ignore PHASEMIS during data phases.
This bit seems to be flakey on U160 controllers acting
in target mode.
aic7xxx_pci.c:
Add support for the 29160C CPCI adapter.
Add definitions for subvendor ID information
available for devices with the "9005" vendor id.
We currently use this information to determine
if a multi-function device doesn't have the second
channel hooked up on a board.
Add rudimentary power mode code so we can put the
controller into the D0 state. In the future this
will be an OSM callback so that in FreeBSD we don't
duplicate functionality provided by the PCI code.
The powerstate code was added after I'd completed
my regression tests on this code.
Only capture "left over BIOS state" if the POWRDN
setting is not set in HCNTRL.
In target mode, don't bother sending incremental
CRC data.
2000-12-20 01:11:37 +00:00
|
|
|
ahc = ahc_alloc(dev, name);
|
2000-09-16 20:02:28 +00:00
|
|
|
if (ahc == NULL)
|
1999-04-23 23:30:22 +00:00
|
|
|
return (ENOMEM);
|
1998-09-15 07:25:33 +00:00
|
|
|
|
2001-01-22 21:03:48 +00:00
|
|
|
ahc_set_unit(ahc, device_get_unit(dev));
|
|
|
|
|
|
2001-07-18 21:39:48 +00:00
|
|
|
/*
|
|
|
|
|
* Should we bother disabling 39Bit addressing
|
|
|
|
|
* based on installed memory?
|
|
|
|
|
*/
|
|
|
|
|
if (sizeof(bus_addr_t) > 4)
|
|
|
|
|
ahc->flags |= AHC_39BIT_ADDRESSING;
|
|
|
|
|
|
1998-09-15 07:25:33 +00:00
|
|
|
/* Allocate a dmatag for our SCB DMA maps */
|
|
|
|
|
/* XXX Should be a child of the PCI bus dma tag */
|
1999-08-16 02:33:46 +00:00
|
|
|
error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
|
1998-09-15 07:25:33 +00:00
|
|
|
/*boundary*/0,
|
2001-07-18 21:39:48 +00:00
|
|
|
(ahc->flags & AHC_39BIT_ADDRESSING)
|
|
|
|
|
? 0x7FFFFFFFFF
|
|
|
|
|
: BUS_SPACE_MAXADDR_32BIT,
|
1998-09-15 07:25:33 +00:00
|
|
|
/*highaddr*/BUS_SPACE_MAXADDR,
|
|
|
|
|
/*filter*/NULL, /*filterarg*/NULL,
|
2002-12-31 04:22:36 +00:00
|
|
|
/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
|
|
|
|
|
/*nsegments*/AHC_NSEG,
|
1998-09-15 07:25:33 +00:00
|
|
|
/*maxsegsz*/AHC_MAXTRANSFER_SIZE,
|
2000-09-16 20:02:28 +00:00
|
|
|
/*flags*/BUS_DMA_ALLOCNOW,
|
|
|
|
|
&ahc->parent_dmat);
|
1998-09-15 07:25:33 +00:00
|
|
|
|
|
|
|
|
if (error != 0) {
|
1999-04-23 23:30:22 +00:00
|
|
|
printf("ahc_pci_attach: Could not allocate DMA tag "
|
|
|
|
|
"- error %d\n", error);
|
1998-09-15 07:25:33 +00:00
|
|
|
ahc_free(ahc);
|
1999-04-23 23:30:22 +00:00
|
|
|
return (ENOMEM);
|
1998-09-15 07:25:33 +00:00
|
|
|
}
|
2000-09-16 20:02:28 +00:00
|
|
|
ahc->dev_softc = dev;
|
|
|
|
|
error = ahc_pci_config(ahc, entry);
|
|
|
|
|
if (error != 0) {
|
1998-09-15 07:25:33 +00:00
|
|
|
ahc_free(ahc);
|
2000-09-16 20:02:28 +00:00
|
|
|
return (error);
|
1998-09-15 07:25:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ahc_attach(ahc);
|
1999-04-23 23:30:22 +00:00
|
|
|
return (0);
|
1998-09-15 07:25:33 +00:00
|
|
|
}
|
|
|
|
|
|
2000-09-16 20:02:28 +00:00
|
|
|
int
|
|
|
|
|
ahc_pci_map_registers(struct ahc_softc *ahc)
|
1998-09-15 07:25:33 +00:00
|
|
|
{
|
2000-09-16 20:02:28 +00:00
|
|
|
struct resource *regs;
|
|
|
|
|
u_int command;
|
|
|
|
|
int regs_type;
|
|
|
|
|
int regs_id;
|
2002-11-30 19:11:44 +00:00
|
|
|
int allow_memio;
|
1998-09-15 07:25:33 +00:00
|
|
|
|
2000-09-16 20:02:28 +00:00
|
|
|
command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
|
|
|
|
|
regs = NULL;
|
|
|
|
|
regs_type = 0;
|
|
|
|
|
regs_id = 0;
|
2002-11-30 19:11:44 +00:00
|
|
|
|
|
|
|
|
/* Retrieve the per-device 'allow_memio' hint */
|
|
|
|
|
if (resource_int_value(device_get_name(ahc->dev_softc),
|
|
|
|
|
device_get_unit(ahc->dev_softc),
|
|
|
|
|
"allow_memio", &allow_memio) != 0) {
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
device_printf(ahc->dev_softc, "Defaulting to MEMIO ");
|
2000-09-22 22:18:05 +00:00
|
|
|
#ifdef AHC_ALLOW_MEMIO
|
2002-11-30 19:11:44 +00:00
|
|
|
if (bootverbose)
|
|
|
|
|
printf("on\n");
|
|
|
|
|
allow_memio = 1;
|
|
|
|
|
#else
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf("off\n");
|
|
|
|
|
allow_memio = 0;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((allow_memio != 0) && (command & PCIM_CMD_MEMEN) != 0) {
|
ahc_eisa.c:
ahc_pci.c:
Add detach support.
Make use of soft allocated on our behalf by newbus.
For PCI devices, disable the mapping type we aren't
using for extra protection from rogue code.
aic7xxx_93cx6.c:
aic7xxx_93cx6.h:
Sync perforce IDs.
aic7xxx_freebsd.c:
Capture the eventhandle returned by EVENTHANDER_REGISTER
so we can kill the handler off during detach.
Use AHC_* constants instead of hard coded numbers in a
few more places.
Test PPR option state when deciding to "really" negotiate
when the CAM_NEGOTIATE flag is passed in a CCB.
Make use of core "ahc_pause_and_flushwork" routine in our
timeout handler rather than re-inventing this code.
Cleanup all of our resources (really!) in ahc_platform_free().
We should be all set to become a module now.
Implement the core ahc_detach() routine shared by all of
the FreeBSD front-ends.
aic7xxx_freebsd.h:
Softc storage for our event handler.
Null implementation for the ahc_platform_flushwork() OSM
callback. FreeBSD doesn't need this as XPT callbacks are
safe from all contexts and are done directly in ahc_done().
aic7xxx_inline.h:
Implement new lazy interrupt scheme. To avoid an extra
PCI bus read, we first check our completion queues to
see if any work has completed. If work is available, we
assume that this is the source of the interrupt and skip
reading INTSTAT. Any remaining interrupt status will be
cleared by a second call to the interrupt handler should
the interrupt line still be asserted. This drops the
interrupt handler down to a single PCI bus read in the
common case of I/O completion. This is the same overhead
as in the not so distant past, but the extra sanity of
perforning a PCI read after clearing the command complete
interrupt and before running the completion queue to avoid
missing command complete interrupts added a cycle.
aic7xxx.c:
During initialization, be sure to initialize all scratch
ram locations before they are read to avoid parity errors.
In this case, we use a new function, ahc_unbusy_tcl() to
initialize the scratch ram busy target table.
Replace instances of ahc_index_busy_tcl() used to unbusy
a tcl without looking at the old value with ahc_unbusy_tcl().
Modify ahc_sent_msg so that it can find single byte messages.
ahc_sent_msg is now used to determine if a transfer negotiation
attempt resulted in a bus free.
Be more careful in filtering out only the SCSI interrupts
of interest in ahc_handle_scsiint.
Rearrange interrupt clearing code to ensure that at least
one PCI transaction occurrs after hitting CLRSINT1 and
writting to CLRINT. CLRSINT1 writes take a bit to
take effect, and the re-arrangement provides sufficient
delay to ensure the write to CLRINT is effective. The
old code might report a spurious interrupt on some "fast"
chipsets.
export ahc-update_target_msg_request for use by OSM code.
If a target does not respond to our ATN request, clear
it once we move to a non-message phase. This avoids
sending a MSG_NOOP in some later message out phase.
Use max lun and max target constants instead of
hard-coded values.
Use softc storage built into our device_t under FreeBSD.
Fix a bug in ahc_free() that caused us to delete
resources that were not allocated.
Clean up any tstate/lstate info in ahc_free().
Clear the powerdown state in ahc_reset() so that
registers can be accessed.
Add a preliminary function for pausing the chip and
processing any posted work.
Add a preliminary suspend and resume functions.
aic7xxx.h:
Limit the number of supported luns to 64. We don't
support information unit transfers, so this is the
maximum that makes sense for these chips.
Add a new flag AHC_ALL_INTERRUPTS that forces the
processing of all interrupt state in a single invokation
of ahc_intr(). When the flag is not set, we use the
lazy interrupt handling scheme.
Add data structures to store controller state while
we are suspended.
Use constants instead of hard coded values where appropriate.
Correct some harmless "unsigned/signed" conflicts.
aic7xxx.seq:
Only perform the SCSIBUSL fix on ULTRA2 or newer controllers.
Older controllers seem to be confused by this.
In target mode, ignore PHASEMIS during data phases.
This bit seems to be flakey on U160 controllers acting
in target mode.
aic7xxx_pci.c:
Add support for the 29160C CPCI adapter.
Add definitions for subvendor ID information
available for devices with the "9005" vendor id.
We currently use this information to determine
if a multi-function device doesn't have the second
channel hooked up on a board.
Add rudimentary power mode code so we can put the
controller into the D0 state. In the future this
will be an OSM callback so that in FreeBSD we don't
duplicate functionality provided by the PCI code.
The powerstate code was added after I'd completed
my regression tests on this code.
Only capture "left over BIOS state" if the POWRDN
setting is not set in HCNTRL.
In target mode, don't bother sending incremental
CRC data.
2000-12-20 01:11:37 +00:00
|
|
|
|
2000-09-16 20:02:28 +00:00
|
|
|
regs_type = SYS_RES_MEMORY;
|
|
|
|
|
regs_id = AHC_PCI_MEMADDR;
|
|
|
|
|
regs = bus_alloc_resource(ahc->dev_softc, regs_type,
|
|
|
|
|
®s_id, 0, ~0, 1, RF_ACTIVE);
|
|
|
|
|
if (regs != NULL) {
|
|
|
|
|
ahc->tag = rman_get_bustag(regs);
|
|
|
|
|
ahc->bsh = rman_get_bushandle(regs);
|
1998-09-15 07:25:33 +00:00
|
|
|
|
2000-01-07 22:53:37 +00:00
|
|
|
/*
|
2000-09-16 20:02:28 +00:00
|
|
|
* Do a quick test to see if memory mapped
|
|
|
|
|
* I/O is functioning correctly.
|
2000-01-07 22:53:37 +00:00
|
|
|
*/
|
2002-11-30 19:11:44 +00:00
|
|
|
if (ahc_pci_test_register_access(ahc) != 0) {
|
2000-09-16 20:02:28 +00:00
|
|
|
device_printf(ahc->dev_softc,
|
|
|
|
|
"PCI Device %d:%d:%d failed memory "
|
|
|
|
|
"mapped test. Using PIO.\n",
|
|
|
|
|
ahc_get_pci_bus(ahc->dev_softc),
|
|
|
|
|
ahc_get_pci_slot(ahc->dev_softc),
|
|
|
|
|
ahc_get_pci_function(ahc->dev_softc));
|
|
|
|
|
bus_release_resource(ahc->dev_softc, regs_type,
|
|
|
|
|
regs_id, regs);
|
|
|
|
|
regs = NULL;
|
ahc_eisa.c:
ahc_pci.c:
Add detach support.
Make use of soft allocated on our behalf by newbus.
For PCI devices, disable the mapping type we aren't
using for extra protection from rogue code.
aic7xxx_93cx6.c:
aic7xxx_93cx6.h:
Sync perforce IDs.
aic7xxx_freebsd.c:
Capture the eventhandle returned by EVENTHANDER_REGISTER
so we can kill the handler off during detach.
Use AHC_* constants instead of hard coded numbers in a
few more places.
Test PPR option state when deciding to "really" negotiate
when the CAM_NEGOTIATE flag is passed in a CCB.
Make use of core "ahc_pause_and_flushwork" routine in our
timeout handler rather than re-inventing this code.
Cleanup all of our resources (really!) in ahc_platform_free().
We should be all set to become a module now.
Implement the core ahc_detach() routine shared by all of
the FreeBSD front-ends.
aic7xxx_freebsd.h:
Softc storage for our event handler.
Null implementation for the ahc_platform_flushwork() OSM
callback. FreeBSD doesn't need this as XPT callbacks are
safe from all contexts and are done directly in ahc_done().
aic7xxx_inline.h:
Implement new lazy interrupt scheme. To avoid an extra
PCI bus read, we first check our completion queues to
see if any work has completed. If work is available, we
assume that this is the source of the interrupt and skip
reading INTSTAT. Any remaining interrupt status will be
cleared by a second call to the interrupt handler should
the interrupt line still be asserted. This drops the
interrupt handler down to a single PCI bus read in the
common case of I/O completion. This is the same overhead
as in the not so distant past, but the extra sanity of
perforning a PCI read after clearing the command complete
interrupt and before running the completion queue to avoid
missing command complete interrupts added a cycle.
aic7xxx.c:
During initialization, be sure to initialize all scratch
ram locations before they are read to avoid parity errors.
In this case, we use a new function, ahc_unbusy_tcl() to
initialize the scratch ram busy target table.
Replace instances of ahc_index_busy_tcl() used to unbusy
a tcl without looking at the old value with ahc_unbusy_tcl().
Modify ahc_sent_msg so that it can find single byte messages.
ahc_sent_msg is now used to determine if a transfer negotiation
attempt resulted in a bus free.
Be more careful in filtering out only the SCSI interrupts
of interest in ahc_handle_scsiint.
Rearrange interrupt clearing code to ensure that at least
one PCI transaction occurrs after hitting CLRSINT1 and
writting to CLRINT. CLRSINT1 writes take a bit to
take effect, and the re-arrangement provides sufficient
delay to ensure the write to CLRINT is effective. The
old code might report a spurious interrupt on some "fast"
chipsets.
export ahc-update_target_msg_request for use by OSM code.
If a target does not respond to our ATN request, clear
it once we move to a non-message phase. This avoids
sending a MSG_NOOP in some later message out phase.
Use max lun and max target constants instead of
hard-coded values.
Use softc storage built into our device_t under FreeBSD.
Fix a bug in ahc_free() that caused us to delete
resources that were not allocated.
Clean up any tstate/lstate info in ahc_free().
Clear the powerdown state in ahc_reset() so that
registers can be accessed.
Add a preliminary function for pausing the chip and
processing any posted work.
Add a preliminary suspend and resume functions.
aic7xxx.h:
Limit the number of supported luns to 64. We don't
support information unit transfers, so this is the
maximum that makes sense for these chips.
Add a new flag AHC_ALL_INTERRUPTS that forces the
processing of all interrupt state in a single invokation
of ahc_intr(). When the flag is not set, we use the
lazy interrupt handling scheme.
Add data structures to store controller state while
we are suspended.
Use constants instead of hard coded values where appropriate.
Correct some harmless "unsigned/signed" conflicts.
aic7xxx.seq:
Only perform the SCSIBUSL fix on ULTRA2 or newer controllers.
Older controllers seem to be confused by this.
In target mode, ignore PHASEMIS during data phases.
This bit seems to be flakey on U160 controllers acting
in target mode.
aic7xxx_pci.c:
Add support for the 29160C CPCI adapter.
Add definitions for subvendor ID information
available for devices with the "9005" vendor id.
We currently use this information to determine
if a multi-function device doesn't have the second
channel hooked up on a board.
Add rudimentary power mode code so we can put the
controller into the D0 state. In the future this
will be an OSM callback so that in FreeBSD we don't
duplicate functionality provided by the PCI code.
The powerstate code was added after I'd completed
my regression tests on this code.
Only capture "left over BIOS state" if the POWRDN
setting is not set in HCNTRL.
In target mode, don't bother sending incremental
CRC data.
2000-12-20 01:11:37 +00:00
|
|
|
} else {
|
|
|
|
|
command &= ~PCIM_CMD_PORTEN;
|
|
|
|
|
ahc_pci_write_config(ahc->dev_softc,
|
|
|
|
|
PCIR_COMMAND,
|
|
|
|
|
command, /*bytes*/1);
|
2000-01-07 22:53:37 +00:00
|
|
|
}
|
1998-09-15 07:25:33 +00:00
|
|
|
}
|
|
|
|
|
}
|
2002-11-30 19:11:44 +00:00
|
|
|
|
2000-09-16 20:02:28 +00:00
|
|
|
if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
|
|
|
|
|
regs_type = SYS_RES_IOPORT;
|
|
|
|
|
regs_id = AHC_PCI_IOADDR;
|
|
|
|
|
regs = bus_alloc_resource(ahc->dev_softc, regs_type,
|
|
|
|
|
®s_id, 0, ~0, 1, RF_ACTIVE);
|
2001-07-18 21:39:48 +00:00
|
|
|
if (regs != NULL) {
|
2001-06-21 16:18:27 +00:00
|
|
|
ahc->tag = rman_get_bustag(regs);
|
|
|
|
|
ahc->bsh = rman_get_bushandle(regs);
|
|
|
|
|
command &= ~PCIM_CMD_MEMEN;
|
|
|
|
|
ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
|
|
|
|
|
command, /*bytes*/1);
|
|
|
|
|
}
|
1998-09-15 07:25:33 +00:00
|
|
|
}
|
2000-09-16 20:02:28 +00:00
|
|
|
if (regs == NULL) {
|
|
|
|
|
device_printf(ahc->dev_softc,
|
|
|
|
|
"can't allocate register resources\n");
|
|
|
|
|
return (ENOMEM);
|
1999-05-14 17:38:07 +00:00
|
|
|
}
|
2001-07-18 21:39:48 +00:00
|
|
|
ahc->platform_data->regs_res_type = regs_type;
|
|
|
|
|
ahc->platform_data->regs_res_id = regs_id;
|
|
|
|
|
ahc->platform_data->regs = regs;
|
1999-05-14 17:38:07 +00:00
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
2000-09-16 20:02:28 +00:00
|
|
|
int
|
|
|
|
|
ahc_pci_map_int(struct ahc_softc *ahc)
|
1999-05-14 17:38:07 +00:00
|
|
|
{
|
2000-09-16 20:02:28 +00:00
|
|
|
int zero;
|
2000-07-18 20:12:14 +00:00
|
|
|
|
2000-09-16 20:02:28 +00:00
|
|
|
zero = 0;
|
|
|
|
|
ahc->platform_data->irq =
|
|
|
|
|
bus_alloc_resource(ahc->dev_softc, SYS_RES_IRQ, &zero,
|
|
|
|
|
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
|
2002-08-31 03:04:08 +00:00
|
|
|
if (ahc->platform_data->irq == NULL) {
|
|
|
|
|
device_printf(ahc->dev_softc,
|
|
|
|
|
"bus_alloc_resource() failed to allocate IRQ\n");
|
2000-09-16 20:02:28 +00:00
|
|
|
return (ENOMEM);
|
2002-08-31 03:04:08 +00:00
|
|
|
}
|
2000-09-16 20:02:28 +00:00
|
|
|
ahc->platform_data->irq_res_type = SYS_RES_IRQ;
|
2002-04-24 16:58:51 +00:00
|
|
|
return (ahc_map_int(ahc));
|
1999-05-14 17:38:07 +00:00
|
|
|
}
|
This is an MFC candidate.
ahc_eisa.c:
Change aic7770_map_int to take an additional irq parameter.
Although we can get the irq from the eisa dev under FreeBSD,
we can't do this under linux, so the OSM interface must supply
this.
ahc_pci.c:
Move ahc_power_state_change() to the OSM. This allows us to
use a platform supplied function that does the same thing.
-current will move to the FreeBSD native API in the near
future.
aic7770.c:
Sync up with core changes to support Linux EISA.
We now store a 2 bit primary channel number rather
than a bit flag that only allows b to be the primary
channel. Adjust for this change.
aic7xxx.c:
Namespace and staticization cleanup. All exported symbols
use an "ahc_" prefix to avoid collisions with other modules.
Correct a logic bug that prevented us from dropping
ATN during some exceptional conditions during message
processing.
Take advantage of a new flag managed by the sequencer
that indicates if an SCB fetch is in progress. If so,
the currently selected SCB needs to be returned to the
free list to prevent an SCB leak. This leak is a rarity
and would only occur if a bus reset or timeout resulting
in a bus reset occurred in the middle of an SCB fetch.
Don't attempt to perform ULTRA transfers on ultra capable
adapters missing the external precision resistor required
for ultra speeds. I've never encountered an adapter
configured this way, but better safe than sorry.
Handle the case of 5MHz user sync rate set as "0" instead of 0x1c
in scratch ram.
If we lookup a period of 0 in our table (async), clear the scsi offset.
aic7xxx.h:
Adjust for the primary channel being represented as
a 2 bit integer in the flags member of the ahc softc.
Cleanup the flags definitions so that comment blocks are
not cramped.
Update seeprom definitions to correctly reflect the fact
that the primary channel is represented as a 2 bit integer.
Add AHC_ULTRA_DIASABLED softc flag to denote controllers
missing the external precision resistor.
aic7xxx.reg:
Add DFCACHETH to the definition of DFSTATUS for completness sake.
Add SEQ_FLAGS2 which currently only contains the SCB_DMA
(SCB DMA in progress) flag.
aic7xxx.seq:
Correct a problem when one lun has a disconnected untagged
transaction and another lun has disconnected tagged transactions.
Just because an entry is found in the untagged table doesn't
mean that it will match. If the match on the lun fails, cleanup
the SCB (return it to the disconnected list or free it), and snoop
for a tag message. Before this change, we reported an unsolicited
reselection. This bug was introduced about a month ago during an
overly aggressive optimization pass on the reselection code.
When cleaning up an SCB, we can't just blindly free the SCB. In
the paging case, if the SCB came off of the disconnected list, its
state may never have been updated in host memory. So, check the
disconnected bit in SCB_CONTROL and return the SCB to the disconnected
list if appropriate.
Manage the SCB_DMA flag of SEQ_FLAGS2.
More carefully shutdown the S/G dma engine in all cases by using
a subroutine. Supposedly not doing this can cause an arbiter hang
on some ULTRA2 chips.
Formatting cleanup.
On some chips, at least the aic7856, the transition from
MREQPEND to HDONE can take a full 4 clock cycles. Test
HDONE one more time to avoid this race. We only want our
FIFO hung recovery code to execute when the engine is
really hung.
aic7xxx_93cx6.c:
Sync perforce ids.
aic7xxx_freebsd.c:
Adjust for the primary channel being a 2 bit integer
rather than a flag for 'B' channel being the primary.
Namespace cleanup.
Unpause the sequencer in one error recovery path that
neglected to do so. This could have caused us to perform
a bus reset when a recovery message might have otherwise been
successful.
aic7xxx_freebsd.h:
Use AHC_PCI_CONFIG for controlling compilation of PCI
support consistently throughout the driver.
Move ahc_power_state_change() to OSM.
aic7xxx_inline.h
Namespace cleanup.
Adjust our interrupt handler so it will work in the edge
interrupt case. We must process all interrupt sources
when the interrupt fires or risk not ever getting an
interrupt again. This involves marking the fact
that we are relying on an edge interrupt in ahc->flags
and checking for this condition in addition to the
AHC_ALL_INTERRUPTS flag. This fixes hangs on the
284X and any other aic7770 installation where level
interrupts are not available.
aic7xxx_pci.c:
Move the powerstate manipulation code into the OSM. Several
OSes now provide this functionality natively.
Take another shot at using the data stored in scratch ram
if the SCB2 signature is correct and no SEEPROM data is
available. In the past this failed if external SCB ram
was configured because the memory port was locked. We
now release the memory port prior to testing the values
in SCB2 and re-acquire it prior to doing termination control.
Adjust for new 2 bit primary channel setting.
Trust the STPWLEVEL setting on v 3.X BIOSes too.
Configure any 785X ID in the same fashion and assume
that any device with a rev id of 1 or higher has the
PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
|
|
|
|
|
|
|
|
void
|
|
|
|
|
ahc_power_state_change(struct ahc_softc *ahc, ahc_power_state new_state)
|
|
|
|
|
{
|
|
|
|
|
uint32_t cap;
|
|
|
|
|
u_int cap_offset;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Traverse the capability list looking for
|
|
|
|
|
* the power management capability.
|
|
|
|
|
*/
|
|
|
|
|
cap = 0;
|
|
|
|
|
cap_offset = ahc_pci_read_config(ahc->dev_softc,
|
|
|
|
|
PCIR_CAP_PTR, /*bytes*/1);
|
|
|
|
|
while (cap_offset != 0) {
|
|
|
|
|
|
|
|
|
|
cap = ahc_pci_read_config(ahc->dev_softc,
|
|
|
|
|
cap_offset, /*bytes*/4);
|
|
|
|
|
if ((cap & 0xFF) == 1
|
|
|
|
|
&& ((cap >> 16) & 0x3) > 0) {
|
|
|
|
|
uint32_t pm_control;
|
|
|
|
|
|
|
|
|
|
pm_control = ahc_pci_read_config(ahc->dev_softc,
|
|
|
|
|
cap_offset + 4,
|
2002-04-24 16:58:51 +00:00
|
|
|
/*bytes*/2);
|
This is an MFC candidate.
ahc_eisa.c:
Change aic7770_map_int to take an additional irq parameter.
Although we can get the irq from the eisa dev under FreeBSD,
we can't do this under linux, so the OSM interface must supply
this.
ahc_pci.c:
Move ahc_power_state_change() to the OSM. This allows us to
use a platform supplied function that does the same thing.
-current will move to the FreeBSD native API in the near
future.
aic7770.c:
Sync up with core changes to support Linux EISA.
We now store a 2 bit primary channel number rather
than a bit flag that only allows b to be the primary
channel. Adjust for this change.
aic7xxx.c:
Namespace and staticization cleanup. All exported symbols
use an "ahc_" prefix to avoid collisions with other modules.
Correct a logic bug that prevented us from dropping
ATN during some exceptional conditions during message
processing.
Take advantage of a new flag managed by the sequencer
that indicates if an SCB fetch is in progress. If so,
the currently selected SCB needs to be returned to the
free list to prevent an SCB leak. This leak is a rarity
and would only occur if a bus reset or timeout resulting
in a bus reset occurred in the middle of an SCB fetch.
Don't attempt to perform ULTRA transfers on ultra capable
adapters missing the external precision resistor required
for ultra speeds. I've never encountered an adapter
configured this way, but better safe than sorry.
Handle the case of 5MHz user sync rate set as "0" instead of 0x1c
in scratch ram.
If we lookup a period of 0 in our table (async), clear the scsi offset.
aic7xxx.h:
Adjust for the primary channel being represented as
a 2 bit integer in the flags member of the ahc softc.
Cleanup the flags definitions so that comment blocks are
not cramped.
Update seeprom definitions to correctly reflect the fact
that the primary channel is represented as a 2 bit integer.
Add AHC_ULTRA_DIASABLED softc flag to denote controllers
missing the external precision resistor.
aic7xxx.reg:
Add DFCACHETH to the definition of DFSTATUS for completness sake.
Add SEQ_FLAGS2 which currently only contains the SCB_DMA
(SCB DMA in progress) flag.
aic7xxx.seq:
Correct a problem when one lun has a disconnected untagged
transaction and another lun has disconnected tagged transactions.
Just because an entry is found in the untagged table doesn't
mean that it will match. If the match on the lun fails, cleanup
the SCB (return it to the disconnected list or free it), and snoop
for a tag message. Before this change, we reported an unsolicited
reselection. This bug was introduced about a month ago during an
overly aggressive optimization pass on the reselection code.
When cleaning up an SCB, we can't just blindly free the SCB. In
the paging case, if the SCB came off of the disconnected list, its
state may never have been updated in host memory. So, check the
disconnected bit in SCB_CONTROL and return the SCB to the disconnected
list if appropriate.
Manage the SCB_DMA flag of SEQ_FLAGS2.
More carefully shutdown the S/G dma engine in all cases by using
a subroutine. Supposedly not doing this can cause an arbiter hang
on some ULTRA2 chips.
Formatting cleanup.
On some chips, at least the aic7856, the transition from
MREQPEND to HDONE can take a full 4 clock cycles. Test
HDONE one more time to avoid this race. We only want our
FIFO hung recovery code to execute when the engine is
really hung.
aic7xxx_93cx6.c:
Sync perforce ids.
aic7xxx_freebsd.c:
Adjust for the primary channel being a 2 bit integer
rather than a flag for 'B' channel being the primary.
Namespace cleanup.
Unpause the sequencer in one error recovery path that
neglected to do so. This could have caused us to perform
a bus reset when a recovery message might have otherwise been
successful.
aic7xxx_freebsd.h:
Use AHC_PCI_CONFIG for controlling compilation of PCI
support consistently throughout the driver.
Move ahc_power_state_change() to OSM.
aic7xxx_inline.h
Namespace cleanup.
Adjust our interrupt handler so it will work in the edge
interrupt case. We must process all interrupt sources
when the interrupt fires or risk not ever getting an
interrupt again. This involves marking the fact
that we are relying on an edge interrupt in ahc->flags
and checking for this condition in addition to the
AHC_ALL_INTERRUPTS flag. This fixes hangs on the
284X and any other aic7770 installation where level
interrupts are not available.
aic7xxx_pci.c:
Move the powerstate manipulation code into the OSM. Several
OSes now provide this functionality natively.
Take another shot at using the data stored in scratch ram
if the SCB2 signature is correct and no SEEPROM data is
available. In the past this failed if external SCB ram
was configured because the memory port was locked. We
now release the memory port prior to testing the values
in SCB2 and re-acquire it prior to doing termination control.
Adjust for new 2 bit primary channel setting.
Trust the STPWLEVEL setting on v 3.X BIOSes too.
Configure any 785X ID in the same fashion and assume
that any device with a rev id of 1 or higher has the
PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
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pm_control &= ~0x3;
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pm_control |= new_state;
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ahc_pci_write_config(ahc->dev_softc,
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cap_offset + 4,
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pm_control, /*bytes*/2);
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break;
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}
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cap_offset = (cap >> 8) & 0xFF;
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}
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}
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