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94 lines
3.4 KiB
C
94 lines
3.4 KiB
C
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/*-
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* Copyright 2015 Alexander Kabaev <kan@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MIPS_INGENIC_JZ4780_CLK_H
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#define _MIPS_INGENIC_JZ4780_CLK_H
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_gate.h>
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/* Convenience bitfiled manipulation macros */
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#define REG_MSK(field) (((1u << field ## _WIDTH) - 1) << field ##_SHIFT)
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#define REG_VAL(field, val) ((val) << field ##_SHIFT)
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#define REG_CLR(reg, field) ((reg) & ~REG_MSK(field))
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#define REG_GET(reg, field) (((reg) & REG_MSK(field)) >> field ##_SHIFT)
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#define REG_SET(reg, field, val) (REG_CLR(reg, field) | REG_VAL(field, val))
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/* Common clock macros */
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#define CLK_LOCK(_sc) mtx_lock((_sc)->clk_mtx)
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#define CLK_UNLOCK(_sc) mtx_unlock((_sc)->clk_mtx)
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#define CLK_WR_4(_sc, off, val) bus_write_4((_sc)->clk_res, (off), (val))
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#define CLK_RD_4(_sc, off) bus_read_4((_sc)->clk_res, (off))
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struct jz4780_clk_mux_descr {
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uint16_t mux_reg;
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uint16_t mux_shift: 5;
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uint16_t mux_bits: 5;
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uint16_t mux_map: 4; /* Map into mux space */
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};
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struct jz4780_clk_div_descr {
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uint16_t div_reg;
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uint16_t div_shift: 5;
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uint16_t div_bits: 5;
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uint16_t div_lg: 5;
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int div_ce_bit: 6; /* -1, if CE bit is not present */
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int div_st_bit: 6; /* Can be negative */
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int div_busy_bit: 6; /* Can be negative */
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};
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struct jz4780_clk_descr {
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uint16_t clk_id: 6;
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uint16_t clk_type: 3;
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int clk_gate_bit: 7; /* Can be negative */
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struct jz4780_clk_mux_descr clk_mux;
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struct jz4780_clk_div_descr clk_div;
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const char *clk_name;
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const char *clk_pnames[4];
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};
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/* clk_type bits */
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#define CLK_MASK_GATE 0x01
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#define CLK_MASK_DIV 0x02
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#define CLK_MASK_MUX 0x04
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extern int jz4780_clk_gen_register(struct clkdom *clkdom,
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const struct jz4780_clk_descr *descr, struct mtx *dev_mtx,
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struct resource *mem_res);
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extern int jz4780_clk_pll_register(struct clkdom *clkdom,
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struct clknode_init_def *clkdef, struct mtx *dev_mtx,
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struct resource *mem_res, uint32_t mem_reg);
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extern int jz4780_clk_otg_register(struct clkdom *clkdom,
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struct clknode_init_def *clkdef, struct mtx *dev_mtx,
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struct resource *mem_res);
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#endif /* _MIPS_INGENIC_JZ4780_CLK_PLL_H */
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