2009-01-26 14:00:50 +00:00
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.\"
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.\" Copyright (C) 2008-2009 Semihalf, Michal Hajduk and Bartlomiej Sieka
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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2019-05-22 21:06:10 +00:00
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.Dd May 22, 2019
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2009-01-26 14:00:50 +00:00
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.Dt I2C 8
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.Os
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.Sh NAME
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.Nm i2c
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2012-03-29 05:02:12 +00:00
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.Nd test I2C bus and slave devices
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2009-01-26 14:00:50 +00:00
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.Sh SYNOPSIS
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.Nm
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.Cm -a Ar address
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.Op Fl f Ar device
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.Op Fl d Ar r|w
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2021-05-12 20:01:14 +00:00
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.Op Fl w Ar 0|8|16|16LE|16BE
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2009-01-26 14:00:50 +00:00
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.Op Fl o Ar offset
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.Op Fl c Ar count
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2019-05-22 21:06:10 +00:00
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.Op Fl m Ar tr|ss|rs|no
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2009-01-26 14:00:50 +00:00
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.Op Fl b
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.Op Fl v
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.Nm
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2021-05-19 18:56:59 +00:00
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.Cm -h
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.Nm
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.Cm -i
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2009-01-26 14:00:50 +00:00
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.Op Fl v
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2021-05-19 18:56:59 +00:00
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.Op Ar cmd ...
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.Op Ar -
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2009-01-26 14:00:50 +00:00
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.Nm
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.Cm -r
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.Op Fl f Ar device
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.Op Fl v
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2021-05-19 18:56:59 +00:00
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.Nm
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.Cm -s
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.Op Fl f Ar device
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.Op Fl n Ar skip_addr
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.Op Fl v
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2009-01-26 14:00:50 +00:00
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.Sh DESCRIPTION
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The
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.Nm
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2021-05-19 18:56:59 +00:00
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utility can be used to perform raw data transfers (read or write) to devices
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on an I2C bus.
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2020-10-09 14:03:45 +00:00
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It can also scan the bus for available devices and reset the I2C controller.
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2009-01-26 14:00:50 +00:00
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.Pp
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The options are as follows:
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.Bl -tag -width ".Fl d Ar direction"
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.It Fl a Ar address
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7-bit address on the I2C device to operate on (hex).
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.It Fl b
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binary mode - when performing a read operation, the data read from the device
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2021-05-12 21:34:58 +00:00
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is output in binary format on stdout.
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2009-01-26 14:00:50 +00:00
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.It Fl c Ar count
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2021-05-12 21:34:58 +00:00
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number of bytes to transfer (decimal).
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2009-01-26 14:00:50 +00:00
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.It Fl d Ar r|w
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transfer direction: r - read, w - write.
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2021-05-12 21:34:58 +00:00
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Data to be written is read from stdin as binary bytes.
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2009-01-26 14:00:50 +00:00
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.It Fl f Ar device
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I2C bus to use (default is /dev/iic0).
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2021-05-19 18:56:59 +00:00
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.It Fl i
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Interpreted mode
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.It Fl h
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Help
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2019-05-22 21:06:10 +00:00
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.It Fl m Ar tr|ss|rs|no
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2009-01-26 14:00:50 +00:00
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addressing mode, i.e., I2C bus operations performed after the offset for the
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transfer has been written to the device and before the actual read/write
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2019-05-22 21:06:10 +00:00
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operation.
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.Bl -tag -compact -offset indent
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.It Va tr
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complete-transfer
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.It Va ss
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stop then start
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.It Va rs
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repeated start
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.It Va no
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none
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.El
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Some I2C bus hardware does not provide control over the individual start,
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repeat-start, and stop operations.
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Such hardware can only perform a complete transfer of the offset and the
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data as a single operation.
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The
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.Va tr
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mode creates control structures describing the transfer and submits them
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to the driver as a single complete transaction.
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This mode works on all types of I2C hardware.
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2009-01-26 14:00:50 +00:00
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.It Fl n Ar skip_addr
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2021-05-13 10:55:37 +00:00
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address(es) to be skipped during bus scan.
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One or more addresses ([0x]xx) or ranges of addresses
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([0x]xx-[0x]xx or [0x]xx..[0x]xx) separated by commas or colons.
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2009-01-26 14:00:50 +00:00
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.It Fl o Ar offset
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offset within the device for data transfer (hex).
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2017-10-13 09:21:41 +00:00
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The default is zero.
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Use
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.Dq -w 0
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to disable writing of the offset to the slave.
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2009-01-26 14:00:50 +00:00
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.It Fl r
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reset the controller.
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.It Fl s
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scan the bus for devices.
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.It Fl v
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2012-05-24 02:24:03 +00:00
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be verbose.
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2021-05-12 20:01:14 +00:00
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.It Fl w Ar 0|8|16|16LE|16BE
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2021-05-12 21:34:58 +00:00
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device offset width (in bits).
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2017-10-13 09:21:41 +00:00
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This is used to determine how to pass
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.Ar offset
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specified with
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.Fl o
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to the slave.
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Zero means that the offset is ignored and not passed to the slave at all.
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2023-08-04 11:50:48 +00:00
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The endianness defaults to little-endian.
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2009-01-26 14:00:50 +00:00
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.El
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2021-05-19 18:56:59 +00:00
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.Sh INTERPRETED MODE
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When started with
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.Fl i
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any remaining arguments are interpreted as commands, and
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if the last argument is '-', or there are no arguments,
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commands will (also) be read from stdin.
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.Pp
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Available commands:
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.Bl -tag -compact
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.It 'r' bus address [0|8|16|16LE|16BE] offset count
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Read command, count bytes are read and hexdumped to stdout.
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.It 'w' bus address [0|8|16|16LE|16BE] offset hexstring
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Write command, hexstring (white-space is allowed) is written to device.
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.It 'p' anything
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Print command, the entire line is printed to stdout. (This can be used
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for synchronization.)
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.El
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.Pp
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All numeric fields accept canonical decimal/octal/hex notation.
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.Pp
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Without the
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.Fl v
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option, all errors are fatal with non-zero exit status.
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.Pp
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With the
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.Fl v
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option, no errors are fatal, and all commands will return
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either "OK\en" or "ERROR\en" on stdout.
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In case of error, detailed diagnostics will precede that on stderr.
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.Pp
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Blank lines and lines starting with '#' are ignored.
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2009-01-26 14:00:50 +00:00
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.Sh EXAMPLES
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.Bl -bullet
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.It
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Scan the default bus (/dev/iic0) for devices:
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.Pp
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i2c -s
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.It
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2021-05-13 10:55:37 +00:00
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Scan the default bus (/dev/iic0) for devices and skip addresses
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0x45 to 0x47 (inclusive) and 0x56.
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2009-01-26 14:00:50 +00:00
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.Pp
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2021-05-13 10:55:37 +00:00
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i2c -s -n 0x56,45-47
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2009-01-26 14:00:50 +00:00
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.It
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Read 8 bytes of data from device at address 0x56 (e.g., an EEPROM):
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.Pp
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i2c -a 0x56 -d r -c 8
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.It
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Write 16 bytes of data from file data.bin to device 0x56 at offset 0x10:
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.Pp
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i2c -a 0x56 -d w -c 16 -o 0x10 -b < data.bin
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.It
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Copy 4 bytes between two EEPROMs (0x56 on /dev/iic1 to 0x57 on /dev/iic0):
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.Pp
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i2c -a 0x56 -f /dev/iic1 -d r -c 0x4 -b | i2c -a 0x57 -f /dev/iic0 -d w -c 4 -b
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.It
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Reset the controller:
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.Pp
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i2c -f /dev/iic1 -r
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2021-05-19 18:56:59 +00:00
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.It
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Read 8 bytes at address 24 in an EEPROM:
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.Pp
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i2c -i 'r 0 0x50 16BE 24 8'
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.It
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Read 2x8 bytes at address 24 and 48 in an EEPROM:
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.Pp
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echo 'r 0 0x50 16BE 48 8' | i2c -i 'r 0 0x50 16BE 24 8' -
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2009-01-26 14:00:50 +00:00
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.El
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2021-05-12 21:34:58 +00:00
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.Sh WARNING
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Many systems store critical low-level information in I2C memories, and
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may contain other I2C devices, such as temperature or voltage sensors.
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Reading these can disturb the firmware's operation and writing to them
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can "brick" the hardware.
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2009-01-26 14:00:50 +00:00
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.Sh SEE ALSO
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.Xr iic 4 ,
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.Xr iicbus 4
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2021-05-12 21:34:58 +00:00
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.Xr smbus 4
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2009-01-26 14:00:50 +00:00
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.Sh HISTORY
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The
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.Nm
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utility appeared in
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.Fx 8.0 .
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.Sh AUTHORS
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.An -nosplit
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The
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.Nm
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utility and this manual page were written by
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2014-06-20 09:57:27 +00:00
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.An Bartlomiej Sieka Aq Mt tur@semihalf.com
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2012-03-29 05:02:12 +00:00
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and
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2014-06-20 09:57:27 +00:00
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.An Michal Hajduk Aq Mt mih@semihalf.com .
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2021-05-19 18:56:59 +00:00
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.Pp
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.An Poul-Henning Kamp Aq Mt phk@FreeBSD.org
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added interpreted mode.
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