Add altera_avgen(4), a generic device driver to be used by hard and soft
CPU cores on Altera FPGAs. The device driver allows memory-mapped devices
on Altera's Avalon SoC bus to be exported to userspace via device nodes.
device.hints directories dictate device name, permissible access methods,
physical address and length, and I/O alignment. Devices can be accessed
using read(2)/write(2), but also memory mapped in userspace using mmap(2).
Devices attach directly to the Nexus, as is common for embedded device
drivers; in the future something more mature might be desirable. There is
currently no facility to support directing device-originated interrupts to
userspace.
In the future, this device driver may be renamed to socgen(4), as it can
in principle also be used with other system-on-chip (SoC) busses, such as
Axi on ASICs and FPGAs. However, we have only tested it on Avalon busses
with memory-mapped ROMs, frame buffers, etc.
Sponsored by: DARPA, AFRL
2012-08-25 11:07:43 +00:00
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/*-
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* Copyright (c) 2012 Robert N. M. Watson
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_ALTERA_AVALON_H_
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#define _DEV_ALTERA_AVALON_H_
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struct altera_avgen_softc {
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/*
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* Bus-related fields.
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*/
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device_t avg_dev;
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int avg_unit;
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/*
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* The device node and memory-mapped I/O region.
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*/
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struct cdev *avg_cdev;
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struct resource *avg_res;
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int avg_rid;
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/*
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* Access properties configured by device.hints.
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*/
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u_int avg_flags;
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u_int avg_width;
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};
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/*
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* Various flags extracted from device.hints to configure operations on the
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* device.
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*/
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#define ALTERA_AVALON_FLAG_READ 0x01
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#define ALTERA_AVALON_FLAG_WRITE 0x02
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#define ALTERA_AVALON_FLAG_MMAP_READ 0x04
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#define ALTERA_AVALON_FLAG_MMAP_WRITE 0x08
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#define ALTERA_AVALON_FLAG_MMAP_EXEC 0x10
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#define ALTERA_AVALON_CHAR_READ 'r'
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#define ALTERA_AVALON_CHAR_WRITE 'w'
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#define ALTERA_AVALON_CHAR_EXEC 'x'
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#define ALTERA_AVALON_STR_WIDTH "width"
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#define ALTERA_AVALON_STR_FILEIO "fileio"
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#define ALTERA_AVALON_STR_MMAPIO "mmapio"
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#define ALTERA_AVALON_STR_DEVNAME "devname"
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#define ALTERA_AVALON_STR_DEVUNIT "devunit"
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/*
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* Driver setup routines from the bus attachment/teardown.
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*/
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2013-01-13 16:43:59 +00:00
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int altera_avgen_attach(struct altera_avgen_softc *sc,
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const char *str_fileio, const char *str_mmapio,
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const char *str_devname, int devunit);
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Add altera_avgen(4), a generic device driver to be used by hard and soft
CPU cores on Altera FPGAs. The device driver allows memory-mapped devices
on Altera's Avalon SoC bus to be exported to userspace via device nodes.
device.hints directories dictate device name, permissible access methods,
physical address and length, and I/O alignment. Devices can be accessed
using read(2)/write(2), but also memory mapped in userspace using mmap(2).
Devices attach directly to the Nexus, as is common for embedded device
drivers; in the future something more mature might be desirable. There is
currently no facility to support directing device-originated interrupts to
userspace.
In the future, this device driver may be renamed to socgen(4), as it can
in principle also be used with other system-on-chip (SoC) busses, such as
Axi on ASICs and FPGAs. However, we have only tested it on Avalon busses
with memory-mapped ROMs, frame buffers, etc.
Sponsored by: DARPA, AFRL
2012-08-25 11:07:43 +00:00
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void altera_avgen_detach(struct altera_avgen_softc *sc);
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2013-01-13 16:57:11 +00:00
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extern devclass_t altera_avgen_devclass;
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Add altera_avgen(4), a generic device driver to be used by hard and soft
CPU cores on Altera FPGAs. The device driver allows memory-mapped devices
on Altera's Avalon SoC bus to be exported to userspace via device nodes.
device.hints directories dictate device name, permissible access methods,
physical address and length, and I/O alignment. Devices can be accessed
using read(2)/write(2), but also memory mapped in userspace using mmap(2).
Devices attach directly to the Nexus, as is common for embedded device
drivers; in the future something more mature might be desirable. There is
currently no facility to support directing device-originated interrupts to
userspace.
In the future, this device driver may be renamed to socgen(4), as it can
in principle also be used with other system-on-chip (SoC) busses, such as
Axi on ASICs and FPGAs. However, we have only tested it on Avalon busses
with memory-mapped ROMs, frame buffers, etc.
Sponsored by: DARPA, AFRL
2012-08-25 11:07:43 +00:00
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#endif /* _DEV_ALTERA_AVALON_H_ */
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