1995-01-13 02:23:27 +00:00
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|
|
/*
|
|
|
|
* Product specific probe and attach routines for:
|
1995-09-05 23:53:48 +00:00
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|
* 3940, 2940, aic7870, and aic7850 SCSI controllers
|
1995-01-13 02:23:27 +00:00
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|
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*
|
1996-01-29 03:18:20 +00:00
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* Copyright (c) 1995, 1996 Justin T. Gibbs
|
1995-01-13 02:23:27 +00:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Absolutely no warranty of function or purpose is made by the author
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* Justin T. Gibbs.
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* 4. Modifications may be freely made to this file if the above conditions
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* are met.
|
1995-01-16 16:31:57 +00:00
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*
|
1996-03-11 02:49:48 +00:00
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|
* $Id: aic7870.c,v 1.26 1996/03/10 07:12:48 gibbs Exp $
|
1995-01-13 02:23:27 +00:00
|
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|
*/
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#include <pci.h>
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|
|
#if NPCI > 0
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|
|
#include <sys/param.h>
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|
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#include <sys/systm.h>
|
1995-03-31 14:08:33 +00:00
|
|
|
#include <sys/malloc.h>
|
1995-04-15 21:38:34 +00:00
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|
#include <sys/kernel.h>
|
1996-01-03 06:34:10 +00:00
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|
|
1995-01-13 02:23:27 +00:00
|
|
|
#include <scsi/scsi_all.h>
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|
|
#include <scsi/scsiconf.h>
|
1996-01-03 06:34:10 +00:00
|
|
|
|
1995-02-02 12:36:19 +00:00
|
|
|
#include <pci/pcireg.h>
|
1995-02-02 13:12:18 +00:00
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|
|
#include <pci/pcivar.h>
|
1996-01-03 06:34:10 +00:00
|
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|
|
#include <machine/clock.h>
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|
1995-01-13 02:23:27 +00:00
|
|
|
#include <i386/scsi/aic7xxx.h>
|
1996-01-03 06:34:10 +00:00
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|
#include <i386/scsi/93cx6.h>
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#include <dev/aic7xxx/aic7xxx_reg.h>
|
1995-01-13 02:23:27 +00:00
|
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#define PCI_BASEADR0 PCI_MAP_REG_START
|
1995-10-26 23:58:59 +00:00
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#define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul
|
1996-01-03 06:34:10 +00:00
|
|
|
#define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul
|
1995-10-08 17:46:11 +00:00
|
|
|
#define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul
|
1995-07-04 21:21:33 +00:00
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|
#define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul
|
1996-01-03 06:34:10 +00:00
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#define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul
|
1995-01-13 02:23:27 +00:00
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#define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul
|
1995-10-26 23:58:59 +00:00
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#define PCI_DEVICE_ID_ADAPTEC_AIC7880 0x80789004ul
|
1995-01-22 00:47:50 +00:00
|
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#define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul
|
1995-08-20 03:18:09 +00:00
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|
#define PCI_DEVICE_ID_ADAPTEC_AIC7850 0x50789004ul
|
1995-01-13 02:23:27 +00:00
|
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|
1995-09-05 23:53:48 +00:00
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#define DEVCONFIG 0x40
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#define MPORTMODE 0x00000400ul /* aic7870 only */
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#define RAMPSM 0x00000200ul /* aic7870 only */
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#define VOLSENSE 0x00000100ul
|
1996-01-03 06:34:10 +00:00
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#define SCBRAMSEL 0x00000080ul
|
1995-09-05 23:53:48 +00:00
|
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|
#define MRDCEN 0x00000040ul
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|
|
#define EXTSCBTIME 0x00000020ul /* aic7870 only */
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|
|
#define EXTSCBPEN 0x00000010ul /* aic7870 only */
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|
|
#define BERREN 0x00000008ul
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|
|
#define DACEN 0x00000004ul
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|
#define STPWLEVEL 0x00000002ul
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|
|
#define DIFACTNEGEN 0x00000001ul /* aic7870 only */
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|
|
1996-01-03 06:34:10 +00:00
|
|
|
#define CSIZE_LATTIME 0x0c
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|
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#define CACHESIZE 0x0000003ful /* only 5 bits */
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|
|
#define LATTIME 0x0000ff00ul
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|
|
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|
|
/*
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|
|
* Define the format of the aic78X0 SEEPROM registers (16 bits).
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*
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|
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|
*/
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|
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struct seeprom_config {
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/*
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|
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* SCSI ID Configuration Flags
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|
|
|
*/
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|
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#define CFXFER 0x0007 /* synchronous transfer rate */
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|
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#define CFSYNCH 0x0008 /* enable synchronous transfer */
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|
|
|
#define CFDISC 0x0010 /* enable disconnection */
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|
|
|
#define CFWIDEB 0x0020 /* wide bus device */
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|
|
|
/* UNUSED 0x00C0 */
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|
|
#define CFSTART 0x0100 /* send start unit SCSI command */
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|
|
|
#define CFINCBIOS 0x0200 /* include in BIOS scan */
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|
|
#define CFRNFOUND 0x0400 /* report even if not found */
|
|
|
|
/* UNUSED 0xf800 */
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|
|
|
unsigned short device_flags[16]; /* words 0-15 */
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|
|
|
|
|
|
|
/*
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|
|
|
* BIOS Control Bits
|
|
|
|
*/
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|
|
|
#define CFSUPREM 0x0001 /* support all removeable drives */
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|
|
|
#define CFSUPREMB 0x0002 /* support removeable drives for boot only */
|
|
|
|
#define CFBIOSEN 0x0004 /* BIOS enabled */
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|
|
|
/* UNUSED 0x0008 */
|
|
|
|
#define CFSM2DRV 0x0010 /* support more than two drives */
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|
|
|
/* UNUSED 0x0060 */
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|
|
|
#define CFEXTEND 0x0080 /* extended translation enabled */
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|
|
/* UNUSED 0xff00 */
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|
|
unsigned short bios_control; /* word 16 */
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|
|
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|
|
/*
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|
|
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* Host Adapter Control Bits
|
|
|
|
*/
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|
|
/* UNUSED 0x0001 */
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|
|
#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable (Ultra cards) */
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|
|
|
#define CFSTERM 0x0004 /* SCSI low byte termination (non-wide cards) */
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|
|
|
#define CFWSTERM 0x0008 /* SCSI high byte termination (wide card) */
|
|
|
|
#define CFSPARITY 0x0010 /* SCSI parity */
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|
|
|
/* UNUSED 0x0020 */
|
|
|
|
#define CFRESETB 0x0040 /* reset SCSI bus at IC initialization */
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|
|
|
/* UNUSED 0xff80 */
|
|
|
|
unsigned short adapter_control; /* word 17 */
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|
|
|
|
|
|
|
/*
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|
|
|
* Bus Release, Host Adapter ID
|
|
|
|
*/
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|
|
|
#define CFSCSIID 0x000f /* host adapter SCSI ID */
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|
|
|
/* UNUSED 0x00f0 */
|
|
|
|
#define CFBRTIME 0xff00 /* bus release time */
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|
|
unsigned short brtime_id; /* word 18 */
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|
|
|
|
|
|
|
/*
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|
|
|
* Maximum targets
|
|
|
|
*/
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|
|
|
#define CFMAXTARG 0x00ff /* maximum targets */
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|
|
/* UNUSED 0xff00 */
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|
|
unsigned short max_targets; /* word 19 */
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|
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|
|
unsigned short res_1[11]; /* words 20-30 */
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|
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unsigned short checksum; /* word 31 */
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|
|
};
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|
|
|
1995-01-13 02:23:27 +00:00
|
|
|
static char* aic7870_probe __P((pcici_t tag, pcidi_t type));
|
1995-12-14 09:55:16 +00:00
|
|
|
static void aic7870_attach __P((pcici_t config_id, int unit));
|
1996-01-03 06:34:10 +00:00
|
|
|
static int load_seeprom __P((struct ahc_data *ahc));
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|
|
|
static int acquire_seeprom __P((u_long offset, u_short CS, u_short CK,
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|
|
u_short DO, u_short DI, u_short RDY,
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|
|
|
u_short MS));
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|
|
static void release_seeprom __P((u_long offset, u_short CS, u_short CK,
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|
|
u_short DO, u_short DI, u_short RDY,
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|
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u_short MS));
|
1995-01-13 02:23:27 +00:00
|
|
|
|
1995-09-05 23:53:48 +00:00
|
|
|
static u_char aic3940_count;
|
1995-01-13 02:23:27 +00:00
|
|
|
|
1995-12-14 09:55:16 +00:00
|
|
|
static struct pci_device ahc_pci_driver = {
|
1995-02-02 13:12:18 +00:00
|
|
|
"ahc",
|
1995-01-13 02:23:27 +00:00
|
|
|
aic7870_probe,
|
|
|
|
aic7870_attach,
|
1995-11-05 04:51:58 +00:00
|
|
|
&ahc_unit,
|
1995-03-17 04:27:21 +00:00
|
|
|
NULL
|
1995-01-13 02:23:27 +00:00
|
|
|
};
|
|
|
|
|
1995-11-05 04:51:58 +00:00
|
|
|
DATA_SET (pcidevice_set, ahc_pci_driver);
|
1995-02-02 13:12:18 +00:00
|
|
|
|
1995-05-30 08:16:23 +00:00
|
|
|
static char*
|
1995-01-13 02:23:27 +00:00
|
|
|
aic7870_probe (pcici_t tag, pcidi_t type)
|
1995-05-30 08:16:23 +00:00
|
|
|
{
|
1995-01-13 02:23:27 +00:00
|
|
|
switch(type) {
|
1995-10-26 23:58:59 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_3940U:
|
|
|
|
return ("Adaptec 3940 Ultra SCSI host adapter");
|
|
|
|
break;
|
1995-07-04 21:21:33 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_3940:
|
|
|
|
return ("Adaptec 3940 SCSI host adapter");
|
|
|
|
break;
|
1996-01-03 06:34:10 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_2944U:
|
|
|
|
return ("Adaptec 2944 Ultra SCSI host adapter");
|
|
|
|
break;
|
1995-10-08 17:46:11 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_2940U:
|
|
|
|
return ("Adaptec 2940 Ultra SCSI host adapter");
|
|
|
|
break;
|
1996-01-03 06:34:10 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_2944:
|
|
|
|
return ("Adaptec 2944 SCSI host adapter");
|
|
|
|
break;
|
1995-01-13 02:23:27 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_2940:
|
1995-07-04 21:21:33 +00:00
|
|
|
return ("Adaptec 2940 SCSI host adapter");
|
1995-03-31 14:08:33 +00:00
|
|
|
break;
|
1995-10-26 23:58:59 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_AIC7880:
|
|
|
|
return ("Adaptec aic7880 Ultra SCSI host adapter");
|
|
|
|
break;
|
1995-01-22 00:47:50 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_AIC7870:
|
1995-03-31 14:08:33 +00:00
|
|
|
return ("Adaptec aic7870 SCSI host adapter");
|
|
|
|
break;
|
1995-06-11 19:33:05 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_AIC7850:
|
|
|
|
return ("Adaptec aic7850 SCSI host adapter");
|
|
|
|
break;
|
1995-01-13 02:23:27 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
1995-12-14 09:55:16 +00:00
|
|
|
static void
|
1995-01-13 02:23:27 +00:00
|
|
|
aic7870_attach(config_id, unit)
|
|
|
|
pcici_t config_id;
|
|
|
|
int unit;
|
1995-05-30 08:16:23 +00:00
|
|
|
{
|
|
|
|
u_long io_port;
|
1995-10-26 23:58:59 +00:00
|
|
|
u_long id;
|
1995-03-31 14:08:33 +00:00
|
|
|
unsigned opri = 0;
|
|
|
|
ahc_type ahc_t = AHC_NONE;
|
1995-09-05 23:53:48 +00:00
|
|
|
ahc_flag ahc_f = AHC_FNONE;
|
1995-11-05 04:51:58 +00:00
|
|
|
struct ahc_data *ahc;
|
|
|
|
|
1995-03-31 14:08:33 +00:00
|
|
|
if(!(io_port = pci_conf_read(config_id, PCI_BASEADR0)))
|
1995-01-13 02:23:27 +00:00
|
|
|
return;
|
1995-03-31 14:08:33 +00:00
|
|
|
/*
|
|
|
|
* The first bit of PCI_BASEADR0 is always
|
1995-11-05 04:51:58 +00:00
|
|
|
* set hence we mask it off.
|
1995-03-31 14:08:33 +00:00
|
|
|
*/
|
1995-11-05 04:51:58 +00:00
|
|
|
io_port &= 0xfffffffe;
|
1995-03-31 14:08:33 +00:00
|
|
|
|
1995-10-26 23:58:59 +00:00
|
|
|
switch ((id = pci_conf_read(config_id, PCI_ID_REG))) {
|
|
|
|
case PCI_DEVICE_ID_ADAPTEC_3940U:
|
1995-07-04 21:21:33 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_3940:
|
1995-10-26 23:58:59 +00:00
|
|
|
if (id == PCI_DEVICE_ID_ADAPTEC_3940U)
|
|
|
|
ahc_t = AHC_394U;
|
|
|
|
else
|
|
|
|
ahc_t = AHC_394;
|
1995-09-05 23:53:48 +00:00
|
|
|
aic3940_count++;
|
|
|
|
if(!(aic3940_count & 0x01))
|
|
|
|
/* Even count implies second channel */
|
|
|
|
ahc_f |= AHC_CHNLB;
|
1995-10-26 23:58:59 +00:00
|
|
|
/* Even though it doesn't turn on RAMPS, it has them */
|
|
|
|
ahc_f |= AHC_EXTSCB;
|
1995-07-04 21:21:33 +00:00
|
|
|
break;
|
1996-01-03 06:34:10 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_2944U:
|
1995-10-08 17:46:11 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_2940U:
|
1995-10-26 23:58:59 +00:00
|
|
|
ahc_t = AHC_294U;
|
|
|
|
break;
|
1996-01-03 06:34:10 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_2944:
|
1995-03-31 14:08:33 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_2940:
|
1995-05-30 08:16:23 +00:00
|
|
|
ahc_t = AHC_294;
|
1995-03-31 14:08:33 +00:00
|
|
|
break;
|
1995-10-26 23:58:59 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_AIC7880:
|
|
|
|
ahc_t = AHC_AIC7880;
|
|
|
|
break;
|
1995-03-31 14:08:33 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_AIC7870:
|
|
|
|
ahc_t = AHC_AIC7870;
|
|
|
|
break;
|
1995-06-11 19:33:05 +00:00
|
|
|
case PCI_DEVICE_ID_ADAPTEC_AIC7850:
|
|
|
|
ahc_t = AHC_AIC7850;
|
|
|
|
break;
|
1995-03-31 14:08:33 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
1996-01-03 06:34:10 +00:00
|
|
|
ahc_reset(io_port);
|
|
|
|
|
1995-09-05 23:53:48 +00:00
|
|
|
if(ahc_t & AHC_AIC7870){
|
|
|
|
u_long devconfig = pci_conf_read(config_id, DEVCONFIG);
|
1996-01-03 06:34:10 +00:00
|
|
|
if(devconfig & (RAMPSM)) {
|
1995-09-05 23:53:48 +00:00
|
|
|
/*
|
|
|
|
* External SRAM present. Have the probe walk
|
|
|
|
* the SCBs to see how much SRAM we have and set
|
1996-01-03 06:34:10 +00:00
|
|
|
* the number of SCBs accordingly. We have to
|
|
|
|
* turn off SCBRAMSEL to access the external
|
|
|
|
* SCB SRAM.
|
|
|
|
*
|
|
|
|
* It seems that early versions of the aic7870
|
|
|
|
* didn't use these bits, hence the hack for the
|
|
|
|
* 3940 above. I would guess that recent 3940s
|
|
|
|
* using later aic7870 or aic7880 chips do
|
|
|
|
* actually set RAMPSM.
|
|
|
|
*
|
|
|
|
* The documentation isn't clear, but it sounds
|
|
|
|
* like the value written to devconfig must not
|
|
|
|
* have RAMPSM set. The second sixteen bits of
|
|
|
|
* the register are R/O anyway, so it shouldn't
|
|
|
|
* affect RAMPSM either way.
|
1995-09-05 23:53:48 +00:00
|
|
|
*/
|
1996-01-03 06:34:10 +00:00
|
|
|
devconfig &= ~(RAMPSM|SCBRAMSEL);
|
|
|
|
pci_conf_write(config_id, DEVCONFIG, devconfig);
|
|
|
|
|
1995-09-05 23:53:48 +00:00
|
|
|
ahc_f |= AHC_EXTSCB;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
1996-01-03 06:34:10 +00:00
|
|
|
/*
|
|
|
|
* Ensure that we are using good values for the PCI burst size
|
|
|
|
* and latency timer.
|
|
|
|
*/
|
|
|
|
{
|
|
|
|
u_long csize_lattime = pci_conf_read(config_id, CSIZE_LATTIME);
|
|
|
|
if((csize_lattime & CACHESIZE) == 0) {
|
|
|
|
/* default to 8DWDs. What's the PCI define for this? */
|
|
|
|
csize_lattime |= 8;
|
|
|
|
}
|
|
|
|
if((csize_lattime & LATTIME) == 0) {
|
|
|
|
/* Default to 64 PCLKS (is this a good value?) */
|
|
|
|
/* This may also be availble in the SEEPROM?? */
|
|
|
|
csize_lattime |= (64 << 8);
|
|
|
|
}
|
|
|
|
if(bootverbose)
|
|
|
|
printf("ahc%d: BurstLen = %dDWDs, "
|
|
|
|
"Latency Timer = %dPCLKS\n",
|
1996-01-07 19:26:12 +00:00
|
|
|
unit,
|
1996-01-03 06:34:10 +00:00
|
|
|
csize_lattime & CACHESIZE,
|
|
|
|
(csize_lattime >> 8) & 0xff);
|
1996-01-07 19:26:12 +00:00
|
|
|
pci_conf_write(config_id, CSIZE_LATTIME, csize_lattime);
|
1996-01-03 06:34:10 +00:00
|
|
|
|
|
|
|
}
|
1995-11-05 04:51:58 +00:00
|
|
|
|
|
|
|
if(!(ahc = ahc_alloc(unit, io_port, ahc_t, ahc_f)))
|
|
|
|
return; /* XXX PCI code should take return status */
|
|
|
|
|
1996-01-23 21:48:28 +00:00
|
|
|
if(!(pci_map_int(config_id, ahc_intr, (void *)ahc, &bio_imask))) {
|
1995-11-05 04:51:58 +00:00
|
|
|
ahc_free(ahc);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Protect ourself from spurrious interrupts during
|
|
|
|
* intialization.
|
|
|
|
*/
|
|
|
|
opri = splbio();
|
|
|
|
|
1996-01-03 06:34:10 +00:00
|
|
|
/*
|
|
|
|
* Do aic7870/aic7880/aic7850 specific initialization
|
|
|
|
*/
|
|
|
|
{
|
|
|
|
u_char sblkctl;
|
|
|
|
char *id_string;
|
|
|
|
u_long iobase = ahc->baseport;
|
|
|
|
|
|
|
|
switch(ahc->type) {
|
|
|
|
case AHC_394U:
|
|
|
|
case AHC_294U:
|
|
|
|
case AHC_AIC7880:
|
|
|
|
{
|
|
|
|
id_string = "aic7880 ";
|
|
|
|
load_seeprom(ahc);
|
|
|
|
ahc->maxscbs = 16;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case AHC_394:
|
|
|
|
case AHC_294:
|
|
|
|
case AHC_AIC7870:
|
|
|
|
{
|
|
|
|
id_string = "aic7870 ";
|
|
|
|
load_seeprom(ahc);
|
|
|
|
ahc->maxscbs = 16;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case AHC_AIC7850:
|
|
|
|
{
|
|
|
|
id_string = "aic7850 ";
|
|
|
|
ahc->maxscbs = 3;
|
|
|
|
/* Assume there is no BIOS for these cards? */
|
|
|
|
ahc->flags |= AHC_USEDEFAULTS;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
{
|
|
|
|
printf("ahc: Unknown controller type. Ignoring.\n");
|
|
|
|
return;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
printf("ahc%d: %s", unit, id_string);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Take the LED out of diagnostic mode
|
|
|
|
*/
|
|
|
|
sblkctl = inb(SBLKCTL + iobase);
|
|
|
|
outb(SBLKCTL + iobase, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* I don't know where this is set in the SEEPROM or by the
|
|
|
|
* BIOS, so we default to 100%.
|
|
|
|
*/
|
|
|
|
outb(DSPCISTATUS + iobase, DFTHRSH_100);
|
|
|
|
|
|
|
|
if(ahc->flags & AHC_USEDEFAULTS) {
|
|
|
|
/*
|
|
|
|
* PCI Adapter default setup
|
|
|
|
* Should only be used if the adapter does not have
|
|
|
|
* an SEEPROM and we don't think a BIOS was installed.
|
|
|
|
*/
|
|
|
|
/* Set the host ID */
|
|
|
|
outb(SCSICONF + iobase, 7);
|
|
|
|
/* In case we are a wide card */
|
|
|
|
outb(SCSICONF + 1 + iobase, 7);
|
|
|
|
}
|
|
|
|
|
|
|
|
if(ahc->flags & AHC_EXTSCB) {
|
|
|
|
/*
|
|
|
|
* This adapter has external SCB memory.
|
|
|
|
* Walk the SCBs to determine how many there are.
|
|
|
|
*/
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for(i = 0; i < AHC_SCB_MAX; i++) {
|
|
|
|
outb(SCBPTR + iobase, i);
|
|
|
|
outb(SCBARRAY + iobase, 0xaa);
|
|
|
|
if(inb(SCBARRAY + iobase) == 0xaa){
|
|
|
|
outb(SCBARRAY + iobase, 0x55);
|
|
|
|
if(inb(SCBARRAY + iobase) == 0x55) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
ahc->maxscbs = i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if(ahc_init(ahc)){
|
1995-11-05 04:51:58 +00:00
|
|
|
ahc_free(ahc);
|
1995-03-31 14:08:33 +00:00
|
|
|
splx(opri);
|
1995-11-05 04:51:58 +00:00
|
|
|
return; /* XXX PCI code should take return status */
|
1995-01-13 02:23:27 +00:00
|
|
|
}
|
1995-11-05 04:51:58 +00:00
|
|
|
splx(opri);
|
1996-01-03 06:34:10 +00:00
|
|
|
|
|
|
|
ahc_attach(ahc);
|
1995-01-13 02:23:27 +00:00
|
|
|
return;
|
1995-05-30 08:16:23 +00:00
|
|
|
}
|
1995-01-13 02:23:27 +00:00
|
|
|
|
1996-01-03 06:34:10 +00:00
|
|
|
/*
|
|
|
|
* Read the SEEPROM. Return 0 on failure
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
load_seeprom(ahc)
|
|
|
|
struct ahc_data *ahc;
|
|
|
|
{
|
|
|
|
struct seeprom_config sc;
|
|
|
|
u_short *scarray = (u_short *)≻
|
|
|
|
u_short checksum = 0;
|
|
|
|
u_long iobase = ahc->baseport;
|
1996-03-10 07:12:49 +00:00
|
|
|
u_char scsi_conf;
|
1996-03-11 02:49:48 +00:00
|
|
|
u_char host_id;
|
1996-01-03 06:34:10 +00:00
|
|
|
int have_seeprom, retval;
|
|
|
|
|
|
|
|
if(bootverbose)
|
|
|
|
printf("ahc%d: Reading SEEPROM...", ahc->unit);
|
|
|
|
have_seeprom = acquire_seeprom(iobase + SEECTL, SEECS,
|
|
|
|
SEECK, SEEDO, SEEDI, SEERDY, SEEMS);
|
|
|
|
if (have_seeprom) {
|
|
|
|
have_seeprom = read_seeprom(iobase + SEECTL,
|
|
|
|
(u_short *)&sc,
|
|
|
|
ahc->flags & AHC_CHNLB,
|
|
|
|
sizeof(sc)/2, SEECS, SEECK, SEEDO,
|
|
|
|
SEEDI, SEERDY, SEEMS);
|
|
|
|
release_seeprom(iobase + SEECTL, SEECS, SEECK, SEEDO,
|
|
|
|
SEEDI, SEERDY, SEEMS);
|
|
|
|
if (have_seeprom) {
|
|
|
|
/* Check checksum */
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0;i < (sizeof(sc)/2 - 1);i = i + 1)
|
|
|
|
checksum = checksum + scarray[i];
|
|
|
|
if (checksum != sc.checksum) {
|
|
|
|
printf ("checksum error");
|
|
|
|
have_seeprom = 0;
|
|
|
|
}
|
1996-03-10 07:12:49 +00:00
|
|
|
else if(bootverbose)
|
1996-01-03 06:34:10 +00:00
|
|
|
printf("done.\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!have_seeprom) {
|
|
|
|
printf("\nahc%d: SEEPROM read failed, "
|
|
|
|
"using leftover BIOS values\n", ahc->unit);
|
|
|
|
retval = 0;
|
|
|
|
|
1996-03-11 02:49:48 +00:00
|
|
|
host_id = 0x7;
|
|
|
|
scsi_conf = host_id | ENSPCHK; /* Assume a default */
|
1996-01-03 06:34:10 +00:00
|
|
|
/*
|
|
|
|
* If we happen to be an ULTRA card,
|
|
|
|
* default to non-ultra mode.
|
|
|
|
*/
|
|
|
|
ahc->type &= ~AHC_ULTRA;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
/*
|
|
|
|
* Put the data we've collected down into SRAM
|
|
|
|
* where ahc_init will find it.
|
|
|
|
*/
|
|
|
|
int i;
|
|
|
|
int max_targ = sc.max_targets & CFMAXTARG;
|
|
|
|
|
|
|
|
for(i = 0; i <= max_targ; i++){
|
|
|
|
u_char target_settings;
|
|
|
|
target_settings = (sc.device_flags[i] & CFXFER) << 4;
|
|
|
|
if (sc.device_flags[i] & CFSYNCH)
|
|
|
|
target_settings |= SOFS;
|
|
|
|
if (sc.device_flags[i] & CFWIDEB)
|
|
|
|
target_settings |= WIDEXFER;
|
|
|
|
if (sc.device_flags[i] & CFDISC)
|
|
|
|
ahc->discenable |= (0x01 << i);
|
|
|
|
outb(TARG_SCRATCH+i+iobase, target_settings);
|
|
|
|
}
|
|
|
|
outb(DISC_DSB + iobase, ~(ahc->discenable & 0xff));
|
|
|
|
outb(DISC_DSB + iobase + 1, ~((ahc->discenable >> 8) & 0xff));
|
|
|
|
|
1996-03-11 02:49:48 +00:00
|
|
|
host_id = sc.brtime_id & CFSCSIID;
|
|
|
|
|
|
|
|
scsi_conf = (host_id & 0x7);
|
1996-03-10 07:12:49 +00:00
|
|
|
if(sc.adapter_control & CFSPARITY)
|
|
|
|
scsi_conf |= ENSPCHK;
|
1996-01-03 06:34:10 +00:00
|
|
|
|
|
|
|
if(ahc->type & AHC_ULTRA) {
|
|
|
|
/* Should we enable Ultra mode? */
|
|
|
|
if(!(sc.adapter_control & CFULTRAEN))
|
|
|
|
/* Treat us as a non-ultra card */
|
|
|
|
ahc->type &= ~AHC_ULTRA;
|
|
|
|
}
|
|
|
|
retval = 1;
|
|
|
|
}
|
|
|
|
/* Set the host ID */
|
1996-03-10 07:12:49 +00:00
|
|
|
outb(SCSICONF + iobase, scsi_conf);
|
1996-01-03 06:34:10 +00:00
|
|
|
/* In case we are a wide card */
|
1996-03-10 07:12:49 +00:00
|
|
|
outb(SCSICONF + 1 + iobase, scsi_conf);
|
1996-01-03 06:34:10 +00:00
|
|
|
|
|
|
|
return(retval);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acquire_seeprom(offset, CS, CK, DO, DI, RDY, MS)
|
|
|
|
u_long offset;
|
|
|
|
u_short CS; /* chip select */
|
|
|
|
u_short CK; /* clock */
|
|
|
|
u_short DO; /* data out */
|
|
|
|
u_short DI; /* data in */
|
|
|
|
u_short RDY; /* ready */
|
|
|
|
u_short MS; /* mode select */
|
|
|
|
{
|
|
|
|
int wait;
|
|
|
|
/*
|
|
|
|
* Request access of the memory port. When access is
|
|
|
|
* granted, SEERDY will go high. We use a 1 second
|
|
|
|
* timeout which should be near 1 second more than
|
|
|
|
* is needed. Reason: after the chip reset, there
|
|
|
|
* should be no contention.
|
|
|
|
*/
|
|
|
|
outb(offset, MS);
|
|
|
|
wait = 1000; /* 1 second timeout in msec */
|
|
|
|
while (--wait && ((inb(offset) & RDY) == 0)) {
|
|
|
|
DELAY (1000); /* delay 1 msec */
|
|
|
|
}
|
|
|
|
if ((inb(offset) & RDY) == 0) {
|
|
|
|
outb (offset, 0);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
return(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
release_seeprom(offset, CS, CK, DO, DI, RDY, MS)
|
|
|
|
u_long offset;
|
|
|
|
u_short CS; /* chip select */
|
|
|
|
u_short CK; /* clock */
|
|
|
|
u_short DO; /* data out */
|
|
|
|
u_short DI; /* data in */
|
|
|
|
u_short RDY; /* ready */
|
|
|
|
u_short MS; /* mode select */
|
|
|
|
{
|
|
|
|
/* Release access to the memory port and the serial EEPROM. */
|
|
|
|
outb(offset, 0);
|
|
|
|
}
|
|
|
|
|
1995-01-13 02:23:27 +00:00
|
|
|
#endif /* NPCI > 0 */
|