2001-02-07 19:57:40 +00:00
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/*-
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* Copyright (c) 2001 Semen Ustimenko (semenu@FreeBSD.org)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_ACPHYREG_H_
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#define _DEV_MII_ACPHYREG_H_
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/*
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* Register definitions for the Altima Communications AC101
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*/
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#define MII_ACPHY_POL 0x10 /* Polarity int level */
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/* High byte is interrupt mask register */
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#define MII_ACPHY_INT 0x11 /* Interrupt control/status */
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#define AC_INT_ACOMP 0x0001 /* Autoneg complete */
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#define AC_INT_REM_FLT 0x0002 /* Remote fault */
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#define AC_INT_LINK_DOWN 0x0004 /* Link not OK */
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#define AC_INT_LP_ACK 0x0008 /* FLP ack recved */
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#define AC_INT_PD_FLT 0x0010 /* Parallel detect fault */
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#define AC_INT_PAGE_RECV 0x0020 /* New page recved */
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#define AC_INT_RX_ER 0x0040 /* RX_ER transitions high */
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#define AC_INT_JAB 0x0080 /* Jabber detected */
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#define MII_ACPHY_DIAG 0x12 /* Diagnostic */
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#define AC_DIAG_RX_LOCK 0x0100
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#define AC_DIAG_RX_PASS 0x0200
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#define AC_DIAG_SPEED 0x0400 /* Aneg speed result */
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#define AC_DIAG_DUPLEX 0x0800 /* Aneg duplex result */
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#define MII_ACPHY_PWRLOOP 0x13 /* Power/Loopback */
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#define MII_ACPHY_CBLMEAS 0x14 /* Cable meas. */
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#define MII_ACPHY_MCTL 0x15 /* Mode control */
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#define AC_MCTL_FX_SEL 0x0001 /* FX mode */
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2007-01-12 22:58:04 +00:00
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#define AC_MCTL_BYP_PCS 0x0002 /* Bypass PCS */
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#define AC_MCTL_SCRMBL 0x0004 /* Data scrambling */
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#define AC_MCTL_REM_LOOP 0x0008 /* Remote loopback */
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#define AC_MCTL_DIS_WDT 0x0010 /* Disable watchdog timer */
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#define AC_MCTL_DIS_REC 0x0020 /* Disable recv error counter */
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#define AC_MCTL_REC_FULL 0x0040 /* Recv error counter full */
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#define AC_MCTL_FRC_FEF 0x0080 /* Force Far End Fault Insert. */
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#define AC_MCTL_DIS_FEF 0x0100 /* Disable FEF Insertion */
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#define AC_MCTL_LED_SEL 0x0200 /* Compat LED config */
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#define AC_MCTL_ALED_SEL 0x0400 /* ActLED RX&TX - RX only */
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#define AC_MCTL_10BT_SEL 0x0800 /* Enable 7-wire interface */
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#define AC_MCTL_DIS_JAB 0x1000 /* Disable jabber */
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#define AC_MCTL_FRC_LINK 0x2000 /* Force TX link up */
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#define AC_MCTL_DIS_NLP 0x4000 /* Disable NLP check */
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2001-02-07 19:57:40 +00:00
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#define MII_ACPHY_REC 0x18 /* Recv error counter */
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#endif /* _DEV_MII_ACPHYREG_H_ */
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