mirror of
https://git.FreeBSD.org/src.git
synced 2025-01-01 12:19:28 +00:00
Add support for Allwinner H3 EMAC.
H3 EMAC is the same as A83T/A64 except the SoC includes an (optional) internal 10/100 PHY. Both internal and external PHYs are supported on H3 with this driver.
This commit is contained in:
Jared McNeill
parent
143d321a30
commit
01a469b860
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=302939
@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/sockio.h>
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#include <sys/module.h>
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#include <sys/taskqueue.h>
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#include <sys/gpio.h>
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#include <net/bpf.h>
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#include <net/if.h>
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@ -69,9 +70,10 @@ __FBSDID("$FreeBSD$");
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#include <dev/extres/regulator/regulator.h>
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#include "miibus_if.h"
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#include "gpio_if.h"
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#define RD4(sc, reg) bus_read_4((sc)->res[0], (reg))
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#define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
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#define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
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#define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
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#define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
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@ -101,6 +103,25 @@ __FBSDID("$FreeBSD$");
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#define TX_INTERVAL_DEFAULT 64
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#define RX_BATCH_DEFAULT 64
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/* syscon EMAC clock register */
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#define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */
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#define EMAC_CLK_EPHY_ADDR_SHIFT 20
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#define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */
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#define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */
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#define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */
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#define EMAC_CLK_RMII_EN (1 << 13)
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#define EMAC_CLK_ETXDC (0x7 << 10)
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#define EMAC_CLK_ETXDC_SHIFT 10
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#define EMAC_CLK_ERXDC (0x1f << 5)
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#define EMAC_CLK_ERXDC_SHIFT 5
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#define EMAC_CLK_PIT (0x1 << 2)
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#define EMAC_CLK_PIT_MII (0 << 2)
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#define EMAC_CLK_PIT_RGMII (1 << 2)
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#define EMAC_CLK_SRC (0x3 << 0)
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#define EMAC_CLK_SRC_MII (0 << 0)
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#define EMAC_CLK_SRC_EXT_RGMII (1 << 0)
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#define EMAC_CLK_SRC_RGMII (2 << 0)
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/* Burst length of RX and TX DMA transfers */
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static int awg_burst_len = BURST_LEN_DEFAULT;
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TUNABLE_INT("hw.awg.burst_len", &awg_burst_len);
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@ -121,8 +142,14 @@ TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval);
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static int awg_rx_batch = RX_BATCH_DEFAULT;
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TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch);
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enum awg_type {
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EMAC_A83T = 1,
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EMAC_H3,
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};
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun8i-a83t-emac", 1 },
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{ "allwinner,sun8i-a83t-emac", EMAC_A83T },
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{ "allwinner,sun8i-h3-emac", EMAC_H3 },
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{ NULL, 0 }
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};
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@ -151,8 +178,15 @@ struct awg_rxring {
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u_int cur;
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};
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enum {
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_RES_EMAC,
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_RES_IRQ,
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_RES_SYSCON,
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_RES_NITEMS
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};
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struct awg_softc {
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struct resource *res[2];
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struct resource *res[_RES_NITEMS];
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struct mtx mtx;
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if_t ifp;
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device_t miibus;
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@ -162,6 +196,7 @@ struct awg_softc {
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u_int mdc_div_ratio_m;
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int link;
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int if_flags;
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enum awg_type type;
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struct awg_txring tx;
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struct awg_rxring rx;
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@ -170,6 +205,7 @@ struct awg_softc {
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static struct resource_spec awg_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
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{ -1, 0 }
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};
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@ -1016,49 +1052,73 @@ awg_ioctl(if_t ifp, u_long cmd, caddr_t data)
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}
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static int
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awg_setup_extres(device_t dev)
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awg_setup_phy(device_t dev)
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{
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struct awg_softc *sc;
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hwreset_t rst_ahb;
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clk_t clk_ahb, clk_tx, clk_tx_parent;
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regulator_t reg;
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clk_t clk_tx, clk_tx_parent;
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const char *tx_parent_name;
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char *phy_type;
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phandle_t node;
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uint64_t freq;
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int error, div;
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uint32_t reg, tx_delay, rx_delay;
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int error;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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rst_ahb = NULL;
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clk_ahb = NULL;
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clk_tx = NULL;
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clk_tx_parent = NULL;
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reg = NULL;
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phy_type = NULL;
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/* Get AHB clock and reset resources */
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error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb);
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if (error != 0) {
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device_printf(dev, "cannot get ahb reset\n");
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goto fail;
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}
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error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb);
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if (error != 0) {
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device_printf(dev, "cannot get ahb clock\n");
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goto fail;
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}
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/* Configure PHY for MII or RGMII mode */
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if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type)) {
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if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type) == 0)
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return (0);
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if (bootverbose)
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device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type,
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sc->res[_RES_SYSCON] != NULL ? "reg" : "clk");
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if (sc->res[_RES_SYSCON] != NULL) {
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reg = bus_read_4(sc->res[_RES_SYSCON], 0);
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reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);
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if (strcmp(phy_type, "rgmii") == 0)
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reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;
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else if (strcmp(phy_type, "rmii") == 0)
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reg |= EMAC_CLK_RMII_EN;
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else
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reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII;
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if (OF_getencprop(node, "tx-delay", &tx_delay,
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sizeof(tx_delay)) > 0) {
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reg &= ~EMAC_CLK_ETXDC;
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reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT);
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}
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if (OF_getencprop(node, "rx-delay", &rx_delay,
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sizeof(rx_delay)) > 0) {
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reg &= ~EMAC_CLK_ERXDC;
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reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT);
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}
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if (sc->type == EMAC_H3) {
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if (OF_hasprop(node, "allwinner,use-internal-phy")) {
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reg |= EMAC_CLK_EPHY_SELECT;
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reg &= ~EMAC_CLK_EPHY_SHUTDOWN;
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if (OF_hasprop(node,
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"allwinner,leds-active-low"))
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reg |= EMAC_CLK_EPHY_LED_POL;
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else
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reg &= ~EMAC_CLK_EPHY_LED_POL;
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/* Set internal PHY addr to 1 */
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reg &= ~EMAC_CLK_EPHY_ADDR;
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reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT);
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} else {
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reg &= ~EMAC_CLK_EPHY_SELECT;
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}
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}
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if (bootverbose)
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device_printf(dev, "PHY type: %s\n", phy_type);
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device_printf(dev, "EMAC clock: 0x%08x\n", reg);
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bus_write_4(sc->res[_RES_SYSCON], 0, reg);
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} else {
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if (strcmp(phy_type, "rgmii") == 0)
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tx_parent_name = "emac_int_tx";
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else
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tx_parent_name = "mii_phy_tx";
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OF_prop_free(phy_type);
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/* Get the TX clock */
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error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx);
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@ -1090,12 +1150,63 @@ awg_setup_extres(device_t dev)
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}
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}
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/* Enable AHB clock */
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error = 0;
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fail:
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OF_prop_free(phy_type);
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return (error);
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}
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static int
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awg_setup_extres(device_t dev)
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{
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struct awg_softc *sc;
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hwreset_t rst_ahb, rst_ephy;
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clk_t clk_ahb, clk_ephy;
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regulator_t reg;
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phandle_t node;
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uint64_t freq;
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int error, div;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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rst_ahb = rst_ephy = NULL;
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clk_ahb = clk_ephy = NULL;
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reg = NULL;
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/* Get AHB clock and reset resources */
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error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb);
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if (error != 0) {
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device_printf(dev, "cannot get ahb reset\n");
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goto fail;
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}
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if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0)
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rst_ephy = NULL;
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error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb);
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if (error != 0) {
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device_printf(dev, "cannot get ahb clock\n");
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goto fail;
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}
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if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0)
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clk_ephy = NULL;
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/* Configure PHY for MII or RGMII mode */
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if (awg_setup_phy(dev) != 0)
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goto fail;
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/* Enable clocks */
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error = clk_enable(clk_ahb);
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if (error != 0) {
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device_printf(dev, "cannot enable ahb clock\n");
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goto fail;
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}
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if (clk_ephy != NULL) {
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error = clk_enable(clk_ephy);
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if (error != 0) {
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device_printf(dev, "cannot enable ephy clock\n");
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goto fail;
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}
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}
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/* De-assert reset */
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error = hwreset_deassert(rst_ahb);
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@ -1103,6 +1214,13 @@ awg_setup_extres(device_t dev)
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device_printf(dev, "cannot de-assert ahb reset\n");
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goto fail;
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}
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if (rst_ephy != NULL) {
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error = hwreset_deassert(rst_ephy);
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if (error != 0) {
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device_printf(dev, "cannot de-assert ephy reset\n");
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goto fail;
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}
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}
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/* Enable PHY regulator if applicable */
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if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) {
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@ -1135,22 +1253,20 @@ awg_setup_extres(device_t dev)
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}
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if (bootverbose)
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device_printf(dev, "AHB frequency %llu Hz, MDC div: 0x%x\n",
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freq, sc->mdc_div_ratio_m);
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device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n",
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(uintmax_t)freq, sc->mdc_div_ratio_m);
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return (0);
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fail:
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OF_prop_free(phy_type);
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if (reg != NULL)
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regulator_release(reg);
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if (clk_tx_parent != NULL)
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clk_release(clk_tx_parent);
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if (clk_tx != NULL)
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clk_release(clk_tx);
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if (clk_ephy != NULL)
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clk_release(clk_ephy);
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if (clk_ahb != NULL)
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clk_release(clk_ahb);
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if (rst_ephy != NULL)
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hwreset_release(rst_ephy);
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if (rst_ahb != NULL)
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hwreset_release(rst_ahb);
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return (error);
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@ -1226,6 +1342,52 @@ awg_dump_regs(device_t dev)
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}
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#endif
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#define GPIO_ACTIVE_LOW 1
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static int
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awg_phy_reset(device_t dev)
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{
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pcell_t gpio_prop[4], delay_prop[3];
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phandle_t node, gpio_node;
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device_t gpio;
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uint32_t pin, flags;
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uint32_t pin_value;
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node = ofw_bus_get_node(dev);
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if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop,
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sizeof(gpio_prop)) <= 0)
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return (0);
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if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop,
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sizeof(delay_prop)) <= 0)
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return (ENXIO);
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gpio_node = OF_node_from_xref(gpio_prop[0]);
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if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL)
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return (ENXIO);
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if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1,
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gpio_prop + 1, &pin, &flags) != 0)
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return (ENXIO);
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pin_value = GPIO_PIN_LOW;
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if (OF_hasprop(node, "allwinner,reset-active-low"))
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pin_value = GPIO_PIN_HIGH;
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if (flags & GPIO_ACTIVE_LOW)
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pin_value = !pin_value;
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GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
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GPIO_PIN_SET(gpio, pin, pin_value);
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DELAY(delay_prop[0]);
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GPIO_PIN_SET(gpio, pin, !pin_value);
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DELAY(delay_prop[1]);
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GPIO_PIN_SET(gpio, pin, pin_value);
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DELAY(delay_prop[2]);
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return (0);
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}
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static int
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awg_reset(device_t dev)
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{
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@ -1234,6 +1396,12 @@ awg_reset(device_t dev)
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sc = device_get_softc(dev);
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/* Reset PHY if necessary */
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if (awg_phy_reset(dev) != 0) {
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device_printf(dev, "failed to reset PHY\n");
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return (ENXIO);
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}
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/* Soft reset all registers and logic */
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WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
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@ -1431,6 +1599,7 @@ awg_attach(device_t dev)
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int error;
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sc = device_get_softc(dev);
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sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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node = ofw_bus_get_node(dev);
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if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) {
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@ -1461,8 +1630,8 @@ awg_attach(device_t dev)
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return (error);
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/* Install interrupt handler */
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error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
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NULL, awg_intr, sc, &sc->ih);
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error = bus_setup_intr(dev, sc->res[_RES_IRQ],
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INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih);
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if (error != 0) {
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device_printf(dev, "cannot setup interrupt handler\n");
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return (error);
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