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Code Issues Releases Activity

DMAR: move hw.iommu.dmar.{tbl_pagecnt,batch_coalesce} sysctls up one level

Browse Source 
Sponsored by:	Advanced Micro Devices (AMD)
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
This commit is contained in:
Konstantin Belousov 2024-08-24 00:10:14 +03:00
parent 29e2270470
commit 0386b24515
5 changed files with 11 additions and 9 deletions
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2
sys/x86/iommu/intel_ctx.c
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@ -877,7 +877,7 @@ dmar_domain_unload_emit_wait(struct dmar_domain *domain,
if (TAILQ_NEXT(entry, dmamap_link) == NULL)
return (true);
return (domain->batch_no++ % dmar_batch_coalesce == 0);
return (domain->batch_no++ % iommu_qi_batch_coalesce == 0);
}
void

3
sys/x86/iommu/intel_dmar.h
View File

@ -166,6 +166,8 @@ struct dmar_unit {
#define DMAR_BARRIER_RMRR 0
#define DMAR_BARRIER_USEQ 1
SYSCTL_DECL(_hw_iommu_dmar);
struct dmar_unit *dmar_find(device_t dev, bool verbose);
struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid);
struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid);
@ -265,7 +267,6 @@ int dmar_map_ioapic_intr(u_int ioapic_id, u_int cpu, u_int vector, bool edge,
int dmar_unmap_ioapic_intr(u_int ioapic_id, u_int *cookie);
extern int haw;
extern int dmar_batch_coalesce;
extern int dmar_rmrr_enable;
static inline uint32_t

4
sys/x86/iommu/intel_utils.c
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@ -507,7 +507,6 @@ dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id)
DMAR_UNLOCK(dmar);
}
int dmar_batch_coalesce = 100;
struct timespec dmar_hw_timeout = {
.tv_sec = 0,
.tv_nsec = 1000000
@ -546,9 +545,6 @@ dmar_timeout_sysctl(SYSCTL_HANDLER_ARGS)
return (error);
}
SYSCTL_INT(_hw_iommu_dmar, OID_AUTO, batch_coalesce, CTLFLAG_RWTUN,
&dmar_batch_coalesce, 0,
"Number of qi batches between interrupt");
SYSCTL_PROC(_hw_iommu_dmar, OID_AUTO, timeout,
CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 0,
dmar_timeout_sysctl, "QU",

9
sys/x86/iommu/iommu_utils.c
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@ -181,9 +181,14 @@ int iommu_tbl_pagecnt;
SYSCTL_NODE(_hw_iommu, OID_AUTO, dmar, CTLFLAG_RD | CTLFLAG_MPSAFE,
NULL, "");
SYSCTL_INT(_hw_iommu_dmar, OID_AUTO, tbl_pagecnt, CTLFLAG_RD,
SYSCTL_INT(_hw_iommu, OID_AUTO, tbl_pagecnt, CTLFLAG_RD,
&iommu_tbl_pagecnt, 0,
"Count of pages used for DMAR pagetables");
"Count of pages used for IOMMU pagetables");
int iommu_qi_batch_coalesce = 100;
SYSCTL_INT(_hw_iommu, OID_AUTO, batch_coalesce, CTLFLAG_RWTUN,
&iommu_qi_batch_coalesce, 0,
"Number of qi batches between interrupt");
static struct x86_iommu *x86_iommu;

2
sys/x86/iommu/x86_iommu.h
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@ -55,9 +55,9 @@ void iommu_unmap_pgtbl(struct sf_buf *sf);
extern iommu_haddr_t iommu_high;
extern int iommu_tbl_pagecnt;
extern int iommu_qi_batch_coalesce;
SYSCTL_DECL(_hw_iommu);
SYSCTL_DECL(_hw_iommu_dmar);
struct x86_unit_common;