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Correctly handle Intel g33 chips and add support for g45 chips
g33 based chips use a different method of identifying the gtt size. g45 based chips gtt is located in a different area of stolen memory. Approved by: jhb (mentor) MFC after: 2 weeks
This commit is contained in:
Robert Noland
parent
24994b364c
commit
06aaad6aaa
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=183555
@ -70,6 +70,7 @@ enum {
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CHIP_I915, /* 915G/915GM */
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CHIP_I965, /* G965 */
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CHIP_G33, /* G33/Q33/Q35 */
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CHIP_G4X, /* G45/Q45 */
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};
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/* The i810 through i855 have the registers at BAR 1, and the GATT gets
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@ -133,7 +134,7 @@ static const struct agp_i810_match {
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{0x25628086, CHIP_I830, 0x00020000,
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"Intel 82845M (845M GMCH) SVGA controller"},
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{0x35828086, CHIP_I855, 0x00020000,
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"Intel 82852/5"},
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"Intel 82852/855GM SVGA controller"},
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{0x25728086, CHIP_I855, 0x00020000,
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"Intel 82865G (865G GMCH) SVGA controller"},
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{0x25828086, CHIP_I915, 0x00020000,
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@ -154,18 +155,26 @@ static const struct agp_i810_match {
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"Intel G965 SVGA controller"},
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{0x29928086, CHIP_I965, 0x00020000,
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"Intel Q965 SVGA controller"},
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{0x29a28086, CHIP_I965, 0x00020000,
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{0x29A28086, CHIP_I965, 0x00020000,
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"Intel G965 SVGA controller"},
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{0x29b28086, CHIP_G33, 0x00020000,
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{0x29B28086, CHIP_G33, 0x00020000,
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"Intel Q35 SVGA controller"},
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{0x29c28086, CHIP_G33, 0x00020000,
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{0x29C28086, CHIP_G33, 0x00020000,
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"Intel G33 SVGA controller"},
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{0x29d28086, CHIP_G33, 0x00020000,
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{0x29D28086, CHIP_G33, 0x00020000,
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"Intel Q33 SVGA controller"},
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{0x2a028086, CHIP_I965, 0x00020000,
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{0x2A028086, CHIP_I965, 0x00020000,
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"Intel GM965 SVGA controller"},
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{0x2a128086, CHIP_I965, 0x00020000,
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{0x2A128086, CHIP_I965, 0x00020000,
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"Intel GME965 SVGA controller"},
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{0x2A428086, CHIP_I965, 0x00020000,
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"Intel GM45 SVGA controller"},
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{0x2E028086, CHIP_G4X, 0x00020000,
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"Intel 4 Series SVGA controller"},
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{0x2E128086, CHIP_G4X, 0x00020000,
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"Intel Q45 SVGA controller"},
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{0x2E228086, CHIP_G4X, 0x00020000,
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"Intel G45 SVGA controller"},
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{0, 0, 0, NULL}
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};
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@ -377,6 +386,7 @@ agp_i810_attach(device_t dev)
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agp_set_aperture_resource(dev, AGP_I915_GMADR);
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break;
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case CHIP_I965:
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case CHIP_G4X:
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sc->sc_res_spec = agp_i965_res_spec;
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agp_set_aperture_resource(dev, AGP_I915_GMADR);
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break;
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@ -476,7 +486,8 @@ agp_i810_attach(device_t dev)
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gatt->ag_physical = pgtblctl & ~1;
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} else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
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sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33) {
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sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
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sc->chiptype == CHIP_G4X) {
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unsigned int gcc1, pgtblctl, stolen, gtt_size;
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/* Stolen memory is set up at the beginning of the aperture by
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@ -491,7 +502,6 @@ agp_i810_attach(device_t dev)
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gtt_size = 256;
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break;
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case CHIP_I965:
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case CHIP_G33:
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switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
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AGP_I810_PGTBL_SIZE_MASK) {
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case AGP_I810_PGTBL_SIZE_128KB:
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@ -503,6 +513,15 @@ agp_i810_attach(device_t dev)
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case AGP_I810_PGTBL_SIZE_512KB:
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gtt_size = 512;
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break;
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case AGP_I965_PGTBL_SIZE_1MB:
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gtt_size = 1024;
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break;
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case AGP_I965_PGTBL_SIZE_2MB:
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gtt_size = 2048;
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break;
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case AGP_I965_PGTBL_SIZE_1_5MB:
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gtt_size = 1024 + 512;
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break;
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default:
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device_printf(dev, "Bad PGTBL size\n");
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bus_release_resources(dev, sc->sc_res_spec,
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@ -512,6 +531,27 @@ agp_i810_attach(device_t dev)
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return EINVAL;
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}
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break;
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case CHIP_G33:
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gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
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switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
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case AGP_G33_MGGC_GGMS_SIZE_1M:
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gtt_size = 1024;
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break;
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case AGP_G33_MGGC_GGMS_SIZE_2M:
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gtt_size = 2048;
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break;
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default:
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device_printf(dev, "Bad PGTBL size\n");
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bus_release_resources(dev, sc->sc_res_spec,
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sc->sc_res);
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free(gatt, M_AGP);
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agp_generic_detach(dev);
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return EINVAL;
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}
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break;
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case CHIP_G4X:
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gtt_size = 0;
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break;
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default:
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device_printf(dev, "Bad chiptype\n");
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bus_release_resources(dev, sc->sc_res_spec,
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@ -528,28 +568,86 @@ agp_i810_attach(device_t dev)
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stolen = 1024;
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break;
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case AGP_I855_GCC1_GMS_STOLEN_4M:
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stolen = 4096;
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stolen = 4 * 1024;
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break;
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case AGP_I855_GCC1_GMS_STOLEN_8M:
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stolen = 8192;
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stolen = 8 * 1024;
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break;
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case AGP_I855_GCC1_GMS_STOLEN_16M:
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stolen = 16384;
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stolen = 16 * 1024;
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break;
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case AGP_I855_GCC1_GMS_STOLEN_32M:
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stolen = 32768;
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stolen = 32 * 1024;
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break;
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case AGP_I915_GCC1_GMS_STOLEN_48M:
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stolen = 49152;
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if (sc->chiptype == CHIP_I915 ||
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sc->chiptype == CHIP_I965 ||
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sc->chiptype == CHIP_G33 ||
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sc->chiptype == CHIP_G4X) {
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stolen = 48 * 1024;
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} else {
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stolen = 0;
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}
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break;
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case AGP_I915_GCC1_GMS_STOLEN_64M:
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stolen = 65536;
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if (sc->chiptype == CHIP_I915 ||
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sc->chiptype == CHIP_I965 ||
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sc->chiptype == CHIP_G33 ||
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sc->chiptype == CHIP_G4X) {
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stolen = 64 * 1024;
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} else {
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stolen = 0;
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}
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break;
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case AGP_G33_GCC1_GMS_STOLEN_128M:
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stolen = 128 * 1024;
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if (sc->chiptype == CHIP_I965 ||
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sc->chiptype == CHIP_G33 ||
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sc->chiptype == CHIP_G4X) {
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stolen = 128 * 1024;
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} else {
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stolen = 0;
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}
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break;
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case AGP_G33_GCC1_GMS_STOLEN_256M:
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stolen = 256 * 1024;
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if (sc->chiptype == CHIP_I965 ||
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sc->chiptype == CHIP_G33 ||
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sc->chiptype == CHIP_G4X) {
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stolen = 256 * 1024;
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} else {
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stolen = 0;
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}
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break;
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case AGP_G4X_GCC1_GMS_STOLEN_96M:
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if (sc->chiptype == CHIP_I965 ||
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sc->chiptype == CHIP_G4X) {
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stolen = 96 * 1024;
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} else {
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stolen = 0;
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}
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break;
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case AGP_G4X_GCC1_GMS_STOLEN_160M:
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if (sc->chiptype == CHIP_I965 ||
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sc->chiptype == CHIP_G4X) {
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stolen = 160 * 1024;
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} else {
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stolen = 0;
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}
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break;
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case AGP_G4X_GCC1_GMS_STOLEN_224M:
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if (sc->chiptype == CHIP_I965 ||
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sc->chiptype == CHIP_G4X) {
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stolen = 224 * 1024;
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} else {
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stolen = 0;
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}
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break;
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case AGP_G4X_GCC1_GMS_STOLEN_352M:
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if (sc->chiptype == CHIP_I965 ||
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sc->chiptype == CHIP_G4X) {
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stolen = 352 * 1024;
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} else {
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stolen = 0;
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}
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break;
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default:
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device_printf(dev, "unknown memory configuration, "
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@ -560,7 +658,11 @@ agp_i810_attach(device_t dev)
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agp_generic_detach(dev);
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return EINVAL;
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}
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sc->stolen = (stolen - gtt_size - 4) * 1024 / 4096;
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if (sc->chiptype != CHIP_G4X)
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gtt_size += 4;
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sc->stolen = (stolen - gtt_size) * 1024 / 4096;
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if (sc->stolen > 0)
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device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
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device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
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@ -215,7 +215,7 @@
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#define AGP_I855_GCC1_DEV2 0x08
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#define AGP_I855_GCC1_DEV2_ENABLED 0x00
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#define AGP_I855_GCC1_DEV2_DISABLED 0x08
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#define AGP_I855_GCC1_GMS 0x70
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#define AGP_I855_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */
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#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00
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#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10
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#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20
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@ -259,13 +259,27 @@
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#define AGP_I965_MSAC_GMASIZE_128 0x00
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#define AGP_I965_MSAC_GMASIZE_256 0x02
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#define AGP_I965_MSAC_GMASIZE_512 0x06
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#define AGP_I965_PGTBL_SIZE_1MB (3 << 1)
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#define AGP_I965_PGTBL_SIZE_2MB (4 << 1)
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#define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1)
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/*
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* G33 registers
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*/
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#define AGP_G33_MGGC_GGMS_MASK (3 << 8)
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#define AGP_G33_MGGC_GGMS_SIZE_1M (1 << 8)
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#define AGP_G33_MGGC_GGMS_SIZE_2M (2 << 8)
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#define AGP_G33_GCC1_GMS_STOLEN_128M 0x80
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#define AGP_G33_GCC1_GMS_STOLEN_256M 0x90
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/*
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* G4X registers
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*/
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#define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0
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#define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0
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#define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0
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#define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0
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/*
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* NVIDIA nForce/nForce2 registers
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*/
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