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- Handle byte-order issue for non-word accesses to memory mapped

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registers with ar71xx_bus_space_reversed. Note, that byte order
    of values is handled by drivers. bus_spaces fixes only position
    of register in word.
- Replace .hints hack for AR71XX UART with ar71xx_bus_space_reversed.
This commit is contained in:
Oleksandr Tymoshenko 2009-04-19 22:56:35 +00:00
parent 50b3024887
commit 06dfe15065
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/mips/; revision=191289
5 changed files with 221 additions and 5 deletions
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181
sys/mips/atheros/ar71xx_bus_space_reversed.c Normal file
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@ -0,0 +1,181 @@
/*-
* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <mips/atheros/ar71xx_bus_space_reversed.h>
static bs_r_1_proto(reversed);
static bs_r_2_proto(reversed);
static bs_w_1_proto(reversed);
static bs_w_2_proto(reversed);
/*
* Bus space that handles offsets in word for 1/2 bytes read/write access.
* Byte order of values is handled by device drivers itself.
*/
static struct bus_space bus_space_reversed = {
/* cookie */
(void *) 0,
/* mapping/unmapping */
generic_bs_map,
generic_bs_unmap,
generic_bs_subregion,
/* allocation/deallocation */
NULL,
NULL,
/* barrier */
generic_bs_barrier,
/* read (single) */
reversed_bs_r_1,
reversed_bs_r_2,
generic_bs_r_4,
NULL,
/* read multiple */
generic_bs_rm_1,
generic_bs_rm_2,
generic_bs_rm_4,
NULL,
/* read region */
generic_bs_rr_1,
generic_bs_rr_2,
generic_bs_rr_4,
NULL,
/* write (single) */
reversed_bs_w_1,
reversed_bs_w_2,
generic_bs_w_4,
NULL,
/* write multiple */
generic_bs_wm_1,
generic_bs_wm_2,
generic_bs_wm_4,
NULL,
/* write region */
NULL,
generic_bs_wr_2,
generic_bs_wr_4,
NULL,
/* set multiple */
NULL,
NULL,
NULL,
NULL,
/* set region */
NULL,
generic_bs_sr_2,
generic_bs_sr_4,
NULL,
/* copy */
NULL,
generic_bs_c_2,
NULL,
NULL,
/* read (single) stream */
generic_bs_r_1,
generic_bs_r_2,
generic_bs_r_4,
NULL,
/* read multiple stream */
generic_bs_rm_1,
generic_bs_rm_2,
generic_bs_rm_4,
NULL,
/* read region stream */
generic_bs_rr_1,
generic_bs_rr_2,
generic_bs_rr_4,
NULL,
/* write (single) stream */
generic_bs_w_1,
generic_bs_w_2,
generic_bs_w_4,
NULL,
/* write multiple stream */
generic_bs_wm_1,
generic_bs_wm_2,
generic_bs_wm_4,
NULL,
/* write region stream */
NULL,
generic_bs_wr_2,
generic_bs_wr_4,
NULL,
};
bus_space_tag_t ar71xx_bus_space_reversed = &bus_space_reversed;
static uint8_t
reversed_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o)
{
return readb(h + (o &~ 3) + (3 - (o & 3)));
}
static void
reversed_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
{
writeb(h + (o &~ 3) + (3 - (o & 3)), v);
}
static uint16_t
reversed_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o)
{
return readw(h + (o &~ 3) + (2 - (o & 3)));
}
static void
reversed_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
{
writew(h + (o &~ 3) + (2 - (o & 3)), v);
}

33
sys/mips/atheros/ar71xx_bus_space_reversed.h Normal file
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@ -0,0 +1,33 @@
/*-
* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef __AR71XX_BUS_SPACE_REVERSEDH__
#define __AR71XX_BUS_SPACE_REVERSEDH__
extern bus_space_tag_t ar71xx_bus_space_reversed;
#endif /* __AR71XX_BUS_SPACE_REVERSEDH__ */

1
sys/mips/atheros/files.ar71xx
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@ -7,3 +7,4 @@ mips/atheros/ar71xx_pci.c optional pci
mips/atheros/if_arge.c optional arge
mips/atheros/uart_bus_ar71xx.c optional uart
mips/atheros/uart_cpu_ar71xx.c optional uart
mips/atheros/ar71xx_bus_space_reversed.c standard

9
sys/mips/atheros/uart_cpu_ar71xx.c
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@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$");
#include <dev/uart/uart_cpu.h>
#include <mips/atheros/ar71xxreg.h>
#include <mips/atheros/ar71xx_bus_space_reversed.h>
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
@ -54,7 +55,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = MIPS_BUS_SPACE_MEM;
di->bas.bst = &ar71xx_bus_space_reversed;
di->bas.regshft = 2;
/* TODO: calculate proper AHB freq using PLL registers */
di->bas.rclk = 85000000;
@ -64,8 +65,8 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
di->parity = UART_PARITY_NONE;
/* TODO: check if uart_bus_space_io mandatory to set */
uart_bus_space_io = MIPS_BUS_SPACE_IO;
uart_bus_space_mem = MIPS_BUS_SPACE_MEM;
uart_bus_space_io = NULL;
uart_bus_space_mem = &ar71xx_bus_space_reversed;
/*
* FIXME:
* 3 is to compensate big endian, uart operates
@ -73,6 +74,6 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
* highest byte instead of lowest one. Actual fix will involve
* MIPS bus_space fixing.
*/
di->bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR) + 3;
di->bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR);
return (0);
}

2
sys/mips/conf/AR71XX.hints
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@ -7,7 +7,7 @@ hint.apb.0.irq=4
# uart0
hint.uart.0.at="apb0"
# see atheros/uart_cpu_ar71xx.c why +3
hint.uart.0.maddr=0x18020003
hint.uart.0.maddr=0x18020000
hint.uart.0.msize=0x18
hint.uart.0.irq=3