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Code Issues Releases Activity

Add PHY DSP code for BCM5755M.

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Obtained from:	OpenBSD
This commit is contained in:
Jung-uk Kim 2007-02-12 22:51:25 +00:00
parent 1f08a54165
commit 08bf8bb7c1
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=166673
4 changed files with 32 additions and 1 deletions
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5
sys/dev/bge/if_bge.c
View File

@ -1687,6 +1687,8 @@ bge_probe(device_t dev)
device_set_desc_copy(dev, buf);
if (pci_get_subvendor(dev) == DELL_VENDORID)
sc->bge_flags |= BGE_FLAG_NO_3LED;
if (did == BCOM_DEVICEID_BCM5755M)
sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
return (0);
}
t++;
@ -2219,7 +2221,8 @@ bge_attach(device_t dev)
sc->bge_flags |= BGE_FLAG_ADC_BUG;
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
if (BGE_IS_5705_PLUS(sc)) {
if (BGE_IS_5705_PLUS(sc) &&
!(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
sc->bge_asicrev == BGE_ASICREV_BCM5787)
sc->bge_flags |= BGE_FLAG_JITTER_BUG;

1
sys/dev/bge/if_bgereg.h
View File

@ -2463,6 +2463,7 @@ struct bge_softc {
#define BGE_FLAG_5704_A0_BUG 0x00800000
#define BGE_FLAG_JITTER_BUG 0x01000000
#define BGE_FLAG_BER_BUG 0x02000000
#define BGE_FLAG_ADJUST_TRIM 0x04000000
uint32_t bge_chipid;
uint8_t bge_asicrev;
uint8_t bge_chiprev;

23
sys/dev/mii/brgphy.c
View File

@ -101,6 +101,7 @@ static void bcm5401_load_dspcode(struct mii_softc *);
static void bcm5411_load_dspcode(struct mii_softc *);
static void brgphy_fixup_adc_bug(struct mii_softc *);
static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
static void brgphy_fixup_adjust_trim(struct mii_softc *);
static void brgphy_fixup_ber_bug(struct mii_softc *);
static void brgphy_fixup_jitter_bug(struct mii_softc *);
static void brgphy_ethernet_wirespeed(struct mii_softc *);
@ -567,6 +568,26 @@ brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
}
static void
brgphy_fixup_adjust_trim(struct mii_softc *sc)
{
static const struct {
int reg;
uint16_t val;
} dspcode[] = {
{ BRGPHY_MII_AUXCTL, 0x0c00 },
{ BRGPHY_MII_DSP_ADDR_REG, 0x000a },
{ BRGPHY_MII_DSP_RW_PORT, 0x110b },
{ BRGPHY_MII_TEST1, 0x0014 },
{ BRGPHY_MII_AUXCTL, 0x0400 },
{ 0, 0 },
};
int i;
for (i = 0; dspcode[i].reg != 0; i++)
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
}
static void
brgphy_fixup_ber_bug(struct mii_softc *sc)
{
@ -691,6 +712,8 @@ brgphy_reset(struct mii_softc *sc)
brgphy_fixup_adc_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
brgphy_fixup_5704_a0_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
brgphy_fixup_adjust_trim(sc);
if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)
brgphy_fixup_ber_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)

4
sys/dev/mii/brgphyreg.h
View File

@ -261,6 +261,10 @@
#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
#define BRGPHY_IMR_CRCERR 0x0001 /* CEC error */
#define BRGPHY_MII_TEST1 0x1e
#define BRGPHY_TEST1_TRIM_EN 0x0010
#define BRGPHY_TEST1_CRC_EN 0x8000
#define BRGPHY_INTRS \
~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)