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For level triggered interrupts clear the PIC IRR bit when the interrupt pin

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is deasserted. Prior to this change each assertion on a level triggered irq
pin resulted in two interrupts being delivered to the CPU.

Differential Revision:	https://reviews.freebsd.org/D1310
Reviewed by:	tychon
MFC after:	1 week
This commit is contained in:
Neel Natu 2014-12-16 06:33:57 +00:00
parent e01343ccd7
commit 09eced2549
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=275817
1 changed files with 2 additions and 0 deletions
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2
sys/amd64/vmm/io/vatpic.c
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@ -388,6 +388,8 @@ vatpic_set_pinstate(struct vatpic *vatpic, int pin, bool newstate)
} else if (oldcnt == 1 && newcnt == 0) {
/* falling edge */
VATPIC_CTR1(vatpic, "atpic pin%d: deasserted", pin);
if (level)
atpic->request &= ~(1 << (pin & 0x7));
} else {
VATPIC_CTR3(vatpic, "atpic pin%d: %s, ignored, acnt %d",
pin, newstate ? "asserted" : "deasserted", newcnt);