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Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was
not tested. While I'm here, clean up SIOCSIFCAP handler.
This commit is contained in:
Pyun YongHyeon
parent
7968da57dc
commit
0af3989be9
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=212167
@ -147,12 +147,15 @@ static void sis_initl(struct sis_softc *);
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static void sis_intr(void *);
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static int sis_ioctl(struct ifnet *, u_long, caddr_t);
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static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
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static int sis_resume(device_t);
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static int sis_rxeof(struct sis_softc *);
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static void sis_start(struct ifnet *);
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static void sis_startl(struct ifnet *);
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static void sis_stop(struct sis_softc *);
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static int sis_suspend(device_t);
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static void sis_add_sysctls(struct sis_softc *);
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static void sis_watchdog(struct sis_softc *);
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static void sis_wol(struct sis_softc *);
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static struct resource_spec sis_res_spec[] = {
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@ -935,6 +938,9 @@ sis_reset(struct sis_softc *sc)
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if (sc->sis_type == SIS_TYPE_83815) {
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CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
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CSR_WRITE_4(sc, NS_CLKRUN, 0);
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} else {
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/* Disable WOL functions. */
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CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
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}
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}
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@ -971,7 +977,7 @@ sis_attach(device_t dev)
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u_char eaddr[ETHER_ADDR_LEN];
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struct sis_softc *sc;
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struct ifnet *ifp;
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int error = 0, waittime = 0;
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int error = 0, pmc, waittime = 0;
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waittime = 0;
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sc = device_get_softc(dev);
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@ -1147,6 +1153,14 @@ sis_attach(device_t dev)
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ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
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IFQ_SET_READY(&ifp->if_snd);
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if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
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if (sc->sis_type == SIS_TYPE_83815)
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ifp->if_capabilities |= IFCAP_WOL;
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else
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ifp->if_capabilities |= IFCAP_WOL_MAGIC;
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ifp->if_capenable = ifp->if_capabilities;
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}
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/*
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* Do MII setup.
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*/
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@ -2227,7 +2241,7 @@ sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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struct sis_softc *sc = ifp->if_softc;
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struct ifreq *ifr = (struct ifreq *) data;
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struct mii_data *mii;
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int error = 0;
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int error = 0, mask;
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switch (command) {
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case SIOCSIFFLAGS:
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@ -2264,32 +2278,37 @@ sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
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break;
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case SIOCSIFCAP:
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/* ok, disable interrupts */
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SIS_LOCK(sc);
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mask = ifr->ifr_reqcap ^ ifp->if_capenable;
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#ifdef DEVICE_POLLING
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if (ifr->ifr_reqcap & IFCAP_POLLING &&
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!(ifp->if_capenable & IFCAP_POLLING)) {
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error = ether_poll_register(sis_poll, ifp);
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if (error)
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return (error);
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SIS_LOCK(sc);
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/* Disable interrupts */
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CSR_WRITE_4(sc, SIS_IER, 0);
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ifp->if_capenable |= IFCAP_POLLING;
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SIS_UNLOCK(sc);
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return (error);
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}
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if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
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ifp->if_capenable & IFCAP_POLLING) {
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error = ether_poll_deregister(ifp);
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/* Enable interrupts. */
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SIS_LOCK(sc);
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CSR_WRITE_4(sc, SIS_IER, 1);
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ifp->if_capenable &= ~IFCAP_POLLING;
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SIS_UNLOCK(sc);
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return (error);
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if ((mask & IFCAP_POLLING) != 0 &&
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(IFCAP_POLLING & ifp->if_capabilities) != 0) {
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ifp->if_capenable ^= IFCAP_POLLING;
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if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
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error = ether_poll_register(sis_poll, ifp);
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if (error != 0) {
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SIS_UNLOCK(sc);
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break;
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}
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/* Disable interrupts. */
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CSR_WRITE_4(sc, SIS_IER, 0);
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} else {
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error = ether_poll_deregister(ifp);
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/* Enable interrupts. */
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CSR_WRITE_4(sc, SIS_IER, 1);
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}
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}
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#endif /* DEVICE_POLLING */
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if ((mask & IFCAP_WOL) != 0 &&
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(ifp->if_capabilities & IFCAP_WOL) != 0) {
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if ((mask & IFCAP_WOL_UCAST) != 0)
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ifp->if_capenable ^= IFCAP_WOL_UCAST;
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if ((mask & IFCAP_WOL_MCAST) != 0)
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ifp->if_capenable ^= IFCAP_WOL_MCAST;
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if ((mask & IFCAP_WOL_MAGIC) != 0)
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ifp->if_capenable ^= IFCAP_WOL_MAGIC;
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}
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SIS_UNLOCK(sc);
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break;
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default:
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error = ether_ioctl(ifp, command, data);
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@ -2384,13 +2403,8 @@ sis_stop(struct sis_softc *sc)
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static int
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sis_shutdown(device_t dev)
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{
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struct sis_softc *sc;
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sc = device_get_softc(dev);
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SIS_LOCK(sc);
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sis_stop(sc);
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SIS_UNLOCK(sc);
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return (0);
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return (sis_suspend(dev));
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}
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static int
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@ -2401,6 +2415,7 @@ sis_suspend(device_t dev)
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sc = device_get_softc(dev);
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SIS_LOCK(sc);
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sis_stop(sc);
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sis_wol(sc);
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SIS_UNLOCK(sc);
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return (0);
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}
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@ -2422,6 +2437,56 @@ sis_resume(device_t dev)
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return (0);
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}
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static void
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sis_wol(struct sis_softc *sc)
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{
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struct ifnet *ifp;
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uint32_t val;
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uint16_t pmstat;
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int pmc;
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ifp = sc->sis_ifp;
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if ((ifp->if_capenable & IFCAP_WOL) == 0)
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return;
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if (sc->sis_type == SIS_TYPE_83815) {
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/* Reset RXDP. */
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CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
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/* Configure WOL events. */
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CSR_READ_4(sc, NS_WCSR);
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val = 0;
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if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
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val |= NS_WCSR_WAKE_UCAST;
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if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
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val |= NS_WCSR_WAKE_MCAST;
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if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
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val |= NS_WCSR_WAKE_MAGIC;
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CSR_WRITE_4(sc, NS_WCSR, val);
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/* Enable PME and clear PMESTS. */
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val = CSR_READ_4(sc, NS_CLKRUN);
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val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
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CSR_WRITE_4(sc, NS_CLKRUN, val);
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/* Enable silent RX mode. */
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SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
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} else {
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if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
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return;
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val = 0;
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if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
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val |= SIS_PWRMAN_WOL_MAGIC;
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CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
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/* Request PME. */
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pmstat = pci_read_config(sc->sis_dev,
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pmc + PCIR_POWER_STATUS, 2);
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pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
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if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
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pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
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pci_write_config(sc->sis_dev,
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pmc + PCIR_POWER_STATUS, pmstat, 2);
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}
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}
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static void
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sis_add_sysctls(struct sis_softc *sc)
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{
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@ -77,6 +77,7 @@
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/* NS DP83815/6 registers */
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#define NS_IHR 0x1C
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#define NS_CLKRUN 0x3C
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#define NS_WCSR 0x40
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#define NS_SRR 0x58
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#define NS_BMCR 0x80
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#define NS_BMSR 0x84
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@ -99,6 +100,29 @@
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#define NS_CLKRUN_PMEENB 0x00000100
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#define NS_CLNRUN_CLKRUN_ENB 0x00000001
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#define NS_WCSR_WAKE_PHYINTR 0x00000001
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#define NS_WCSR_WAKE_UCAST 0x00000002
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#define NS_WCSR_WAKE_MCAST 0x00000004
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#define NS_WCSR_WAKE_BCAST 0x00000008
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#define NS_WCSR_WAKE_ARP 0x00000010
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#define NS_WCSR_WAKE_PATTERN0 0x00000020
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#define NS_WCSR_WAKE_PATTERN1 0x00000040
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#define NS_WCSR_WAKE_PATTERN2 0x00000080
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#define NS_WCSR_WAKE_PATTERN3 0x00000100
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#define NS_WCSR_WAKE_MAGIC 0x00000200
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#define NS_WCSR_WAKE_MAGIC_SEC 0x00000400
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#define NS_WCSR_DET_MAGIC_SECH 0x00100000
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#define NS_WCSR_DET_PHYINTR 0x00400000
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#define NS_WCSR_DET_UCAST 0x00800000
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#define NS_WCSR_DET_MCAST 0x01000000
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#define NS_WCSR_DET_BCAST 0x02000000
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#define NS_WCSR_DET_ARP 0x04000000
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#define NS_WCSR_DET_PATTERN0 0x08000000
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#define NS_WCSR_DET_PATTERN1 0x10000000
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#define NS_WCSR_DET_PATTERN2 0x20000000
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#define NS_WCSR_DET_PATTERN3 0x40000000
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#define NS_WCSR_DET_MAGIC 0x80000000
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/* NS silicon revisions */
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#define NS_SRR_15C 0x302
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#define NS_SRR_15D 0x403
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@ -303,6 +327,10 @@
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#define NS_FILTADDR_FMEM_LO 0x00000200
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#define NS_FILTADDR_FMEM_HI 0x000003FE
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#define SIS_PWRMAN_WOL_LINK_OFF 0x00000001
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#define SIS_PWRMAN_WOL_LINK_ON 0x00000002
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#define SIS_PWRMAN_WOL_MAGIC 0x00000400
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/*
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* TX/RX DMA descriptor structures.
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*/
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