mirror of
https://git.FreeBSD.org/src.git
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- Reimplement {d,i}tlb_enter() and {d,i}tlb_va_to_pa() in C. There's
no particular reason for them to be implemented in assembler and
having them in C allows easier extension as well as using more C
macros and {d,i}tlb_slot_max rather than hard-coding magic (and
actually spitfire-only) values.
- Fix the compilation of pmap_print_tte().
- Change pmap_print_tlb() to use ldxa() rather than re-rolling it
inline as well as TLB_DAR_SLOT and {d,i}tlb_slot_max rather than
hardcoding magic (and actually spitfire-only) values.
- While at it, suffix the above mentioned functions with "_sun4u" to
underline they're architecture-specific.
- Use __FBSDID and macros instead of magic values in locore.S.
- Remove unused includes and smp_stack in locore.S.
This commit is contained in:
Marius Strobl
parent
68910e7a67
commit
0b1bfc4986
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=181398
@ -4,35 +4,34 @@
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* All rights reserved.
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*
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* As long as the above copyright statement and this notice remain
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* unchanged, you can do what ever you want with this file.
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*
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* $FreeBSD$
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* unchanged, you can do what ever you want with this file.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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#define LOCORE
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#include <machine/asi.h>
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#include <machine/asm.h>
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#include <machine/frame.h>
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#include <machine/fsr.h>
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#include <machine/intr_machdep.h>
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#include <machine/pstate.h>
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#include <machine/smp.h>
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#include <machine/upa.h>
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#define PAGE_SIZE 8192
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#define PAGE_SHIFT 13
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#define SPOFF 2047
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#define STACK_SIZE (2 * PAGE_SIZE)
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ENTRY(_start)
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/* limit interrupts */
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wrpr %g0, 13, %pil
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/* Limit interrupts. */
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wrpr %g0, PIL_TICK - 1, %pil
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/*
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* PSTATE: privileged, interrupts enabled, floating point
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* unit enabled
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*/
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wrpr %g0, PSTATE_PRIV|PSTATE_IE|PSTATE_PEF, %pstate
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wr %g0, 0x4, %fprs
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wrpr %g0, PSTATE_PRIV | PSTATE_IE | PSTATE_PEF, %pstate
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wr %g0, FPRS_FEF, %fprs
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setx stack + STACK_SIZE - SPOFF - CCFSZ, %l7, %l6
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mov %l6, %sp
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@ -40,74 +39,4 @@ ENTRY(_start)
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mov %o4, %o0
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sir
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/*
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* %o0 input VA constant
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* %o1 current iTLB offset
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* %o2 current iTLB TTE tag
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*/
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ENTRY(itlb_va_to_pa)
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clr %o1
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0: ldxa [%o1] ASI_ITLB_TAG_READ_REG, %o2
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cmp %o2, %o0
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bne,a %xcc, 1f
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nop
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/* return PA of matching entry */
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ldxa [%o1] ASI_ITLB_DATA_ACCESS_REG, %o0
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sllx %o0, 23, %o0
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srlx %o0, PAGE_SHIFT+23, %o0
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sllx %o0, PAGE_SHIFT, %o0
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retl
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mov %o0, %o1
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1: cmp %o1, 63<<3
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blu %xcc, 0b
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add %o1, 8, %o1
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clr %o0
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retl
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not %o0
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ENTRY(dtlb_va_to_pa)
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clr %o1
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0: ldxa [%o1] ASI_DTLB_TAG_READ_REG, %o2
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cmp %o2, %o0
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bne,a %xcc, 1f
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nop
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/* return PA of matching entry */
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ldxa [%o1] ASI_DTLB_DATA_ACCESS_REG, %o0
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sllx %o0, 23, %o0
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srlx %o0, PAGE_SHIFT+23, %o0
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sllx %o0, PAGE_SHIFT, %o0
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retl
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mov %o0, %o1
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1: cmp %o1, 63<<3
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blu %xcc, 0b
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add %o1, 8, %o1
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clr %o0
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retl
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not %o0
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/*
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* %o0 = vpn
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* %o1 = tte data
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*/
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ENTRY(itlb_enter)
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rdpr %pstate, %o4
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wrpr %o4, PSTATE_IE, %pstate
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mov AA_IMMU_TAR, %o3
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stxa %o0, [%o3] ASI_IMMU
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stxa %o1, [%g0] ASI_ITLB_DATA_IN_REG
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membar #Sync
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retl
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wrpr %o4, 0, %pstate
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ENTRY(dtlb_enter)
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rdpr %pstate, %o4
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wrpr %o4, PSTATE_IE, %pstate
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mov AA_DMMU_TAR, %o3
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stxa %o0, [%o3] ASI_DMMU
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stxa %o1, [%g0] ASI_DTLB_DATA_IN_REG
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membar #Sync
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retl
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wrpr %o4, 0, %pstate
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.comm stack, STACK_SIZE, 32
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.comm smp_stack, STACK_SIZE, 32
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@ -4,7 +4,7 @@
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* All rights reserved.
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*
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* As long as the above copyright statement and this notice remain
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* unchanged, you can do what ever you want with this file.
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* unchanged, you can do what ever you want with this file.
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*/
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#include <sys/cdefs.h>
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@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/lsu.h>
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#include <machine/metadata.h>
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#include <machine/tte.h>
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#include <machine/tlb.h>
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#include <machine/upa.h>
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#include "bootstrap.h"
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@ -56,10 +57,10 @@ static struct mmu_ops {
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typedef void kernel_entry_t(vm_offset_t mdp, u_long o1, u_long o2, u_long o3,
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void *openfirmware);
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extern void itlb_enter(u_long vpn, u_long data);
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extern void dtlb_enter(u_long vpn, u_long data);
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extern vm_offset_t itlb_va_to_pa(vm_offset_t);
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extern vm_offset_t dtlb_va_to_pa(vm_offset_t);
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static void dtlb_enter_sun4u(u_long vpn, u_long data);
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static vm_offset_t dtlb_va_to_pa_sun4u(vm_offset_t);
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static void itlb_enter_sun4u(u_long vpn, u_long data);
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static vm_offset_t itlb_va_to_pa_sun4u(vm_offset_t);
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extern vm_offset_t md_load(char *, vm_offset_t *);
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static int sparc64_autoload(void);
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static ssize_t sparc64_readin(const int, vm_offset_t, const size_t);
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@ -76,6 +77,13 @@ static vm_offset_t init_heap(void);
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static void tlb_init_sun4u(void);
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static void tlb_init_sun4v(void);
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#ifdef LOADER_DEBUG
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typedef u_int64_t tte_t;
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static void pmap_print_tlb_sun4u(void);
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static void pmap_print_tte_sun4u(tte_t, tte_t);
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#endif
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static struct mmu_ops mmu_ops_sun4u = { tlb_init_sun4u, mmu_mapin_sun4u };
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static struct mmu_ops mmu_ops_sun4v = { tlb_init_sun4v, mmu_mapin_sun4v };
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@ -344,9 +352,8 @@ __elfN(exec)(struct preloaded_file *fp)
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return (error);
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printf("jumping to kernel entry at %#lx.\n", e->e_entry);
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#if 0
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pmap_print_tlb('i');
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pmap_print_tlb('d');
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#if LOADER_DEBUG
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pmap_print_tlb_sun4u();
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#endif
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entry = e->e_entry;
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@ -358,6 +365,64 @@ __elfN(exec)(struct preloaded_file *fp)
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panic("%s: exec returned", __func__);
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}
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static vm_offset_t
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dtlb_va_to_pa_sun4u(vm_offset_t va)
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{
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u_long reg;
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int i;
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for (i = 0; i < dtlb_slot_max; i++) {
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reg = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG);
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if (TLB_TAR_VA(reg) != va)
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continue;
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reg = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG);
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return ((reg & TD_PA_SF_MASK) >> TD_PA_SHIFT);
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}
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return (-1);
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}
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static vm_offset_t
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itlb_va_to_pa_sun4u(vm_offset_t va)
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{
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u_long reg;
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int i;
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for (i = 0; i < itlb_slot_max; i++) {
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reg = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_TAG_READ_REG);
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if (TLB_TAR_VA(reg) != va)
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continue;
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reg = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG);
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return ((reg & TD_PA_SF_MASK) >> TD_PA_SHIFT);
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}
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return (-1);
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}
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static void
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itlb_enter_sun4u(u_long vpn, u_long data)
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{
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u_long reg;
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reg = rdpr(pstate);
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wrpr(pstate, reg & ~PSTATE_IE, 0);
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stxa(AA_IMMU_TAR, ASI_IMMU, vpn);
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stxa(0, ASI_ITLB_DATA_IN_REG, data);
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membar(Sync);
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wrpr(pstate, reg, 0);
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}
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static void
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dtlb_enter_sun4u(u_long vpn, u_long data)
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{
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u_long reg;
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reg = rdpr(pstate);
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wrpr(pstate, reg & ~PSTATE_IE, 0);
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stxa(AA_DMMU_TAR, ASI_DMMU, vpn);
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stxa(0, ASI_DTLB_DATA_IN_REG, data);
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membar(Sync);
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wrpr(pstate, reg, 0);
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}
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static int
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mmu_mapin_sun4u(vm_offset_t va, vm_size_t len)
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{
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@ -371,8 +436,8 @@ mmu_mapin_sun4u(vm_offset_t va, vm_size_t len)
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len += va & PAGE_MASK_4M;
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va &= ~PAGE_MASK_4M;
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while (len) {
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if (dtlb_va_to_pa(va) == (vm_offset_t)-1 ||
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itlb_va_to_pa(va) == (vm_offset_t)-1) {
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if (dtlb_va_to_pa_sun4u(va) == (vm_offset_t)-1 ||
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itlb_va_to_pa_sun4u(va) == (vm_offset_t)-1) {
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/* Allocate a physical page, claim the virtual area */
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if (pa == (vm_offset_t)-1) {
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pa = alloc_phys(PAGE_SIZE_4M, PAGE_SIZE_4M);
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@ -402,8 +467,8 @@ mmu_mapin_sun4u(vm_offset_t va, vm_size_t len)
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itlb_store[itlb_slot].te_va = va;
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dtlb_slot++;
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itlb_slot++;
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dtlb_enter(va, data);
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itlb_enter(va, data);
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dtlb_enter_sun4u(va, data);
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itlb_enter_sun4u(va, data);
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pa = (vm_offset_t)-1;
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}
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len -= len > PAGE_SIZE_4M ? PAGE_SIZE_4M : len;
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@ -617,14 +682,12 @@ exit(int code)
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}
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#ifdef LOADER_DEBUG
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typedef u_int64_t tte_t;
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static const char *page_sizes[] = {
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" 8k", " 64k", "512k", " 4m"
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};
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static void
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pmap_print_tte(tte_t tag, tte_t tte)
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pmap_print_tte_sun4u(tte_t tag, tte_t tte)
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{
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printf("%s %s ",
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@ -638,36 +701,31 @@ pmap_print_tte(tte_t tag, tte_t tte)
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printf(tte & TD_L ? "\e[32mL\e[0m " : " ");
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printf(tte & TD_IE ? "IE " : " ");
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printf(tte & TD_NFO ? "NFO " : " ");
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printf("tag=0x%lx pa=0x%lx va=0x%lx ctx=%ld\n", tag, TD_PA(tte),
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TT_VA(tag), TT_CTX(tag));
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printf("pa=0x%lx va=0x%lx ctx=%ld\n",
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TD_PA(tte), TLB_TAR_VA(tag), TLB_TAR_CTX(tag));
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}
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void
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pmap_print_tlb(char which)
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{
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int i;
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tte_t tte, tag;
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for (i = 0; i < 64*8; i += 8) {
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if (which == 'i') {
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__asm__ __volatile__("ldxa [%1] %2, %0\n" :
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"=r" (tag) : "r" (i),
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"i" (ASI_ITLB_TAG_READ_REG));
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__asm__ __volatile__("ldxa [%1] %2, %0\n" :
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"=r" (tte) : "r" (i),
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"i" (ASI_ITLB_DATA_ACCESS_REG));
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}
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else {
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__asm__ __volatile__("ldxa [%1] %2, %0\n" :
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"=r" (tag) : "r" (i),
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"i" (ASI_DTLB_TAG_READ_REG));
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__asm__ __volatile__("ldxa [%1] %2, %0\n" :
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"=r" (tte) : "r" (i),
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"i" (ASI_DTLB_DATA_ACCESS_REG));
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}
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static void
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pmap_print_tlb_sun4u(void)
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{
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tte_t tag, tte;
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int i;
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for (i = 0; i < itlb_slot_max; i++) {
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tte = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG);
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if (!(tte & TD_V))
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continue;
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printf("%cTLB-%2u: ", which, i>>3);
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pmap_print_tte(tag, tte);
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tag = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_TAG_READ_REG);
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printf("iTLB-%2u: ", i);
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pmap_print_tte_sun4u(tag, tte);
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}
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for (i = 0; i < dtlb_slot_max; i++) {
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tte = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG);
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if (!(tte & TD_V))
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continue;
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tag = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG);
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printf("dTLB-%2u: ", i);
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pmap_print_tte_sun4u(tag, tte);
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}
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}
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#endif
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@ -43,12 +43,16 @@
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#define TD_SIZE_BITS (2)
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#define TD_SOFT2_BITS (9)
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#define TD_DIAG_BITS (9)
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#define TD_PA_BITS (28)
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#define TD_PA_CH_BITS (30)
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#define TD_PA_SF_BITS (28)
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#define TD_PA_BITS TD_PA_SF_BITS
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#define TD_SOFT_BITS (6)
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#define TD_SIZE_MASK ((1UL << TD_SIZE_BITS) - 1)
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#define TD_SOFT2_MASK ((1UL << TD_SOFT2_BITS) - 1)
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#define TD_DIAG_MASK ((1UL << TD_DIAG_BITS) - 1)
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#define TD_PA_CH_MASK ((1UL << TD_PA_CH_BITS) - 1)
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#define TD_PA_SF_MASK ((1UL << TD_PA_SF_BITS) - 1)
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#define TD_PA_MASK ((1UL << TD_PA_BITS) - 1)
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#define TD_SOFT_MASK ((1UL << TD_SOFT_BITS) - 1)
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@ -41,11 +41,15 @@
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#define TD_SOFT2_BITS (9)
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#define TD_DIAG_BITS (9)
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#define TD_PA_CH_BITS (30)
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#define TD_PA_SF_BITS (28)
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#define TD_PA_BITS (42)
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#define TD_SOFT_BITS (6)
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#define TD_SOFT2_MASK ((1UL << TD_SOFT2_BITS) - 1)
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#define TD_DIAG_MASK ((1UL << TD_DIAG_BITS) - 1)
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#define TD_PA_CH_MASK ((1UL << TD_PA_CH_BITS) - 1)
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#define TD_PA_SF_MASK ((1UL << TD_PA_SF_BITS) - 1)
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#define TD_PA_MASK ((1UL << TD_PA_BITS) - 1)
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#define TD_SOFT_MASK ((1UL << TD_SOFT_BITS) - 1)
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