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Add PMRCAP printing and fix earlier CAP_HI.
MFC after: 3 days
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parent
1b57066e8b
commit
0bed3eabc5
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=367659
@ -150,6 +150,36 @@
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#define NVME_AQA_REG_ACQS_SHIFT (16)
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#define NVME_AQA_REG_ACQS_MASK (0xFFF)
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#define NVME_PMRCAP_REG_RDS_SHIFT (3)
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#define NVME_PMRCAP_REG_RDS_MASK (0x1)
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#define NVME_PMRCAP_REG_WDS_SHIFT (4)
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#define NVME_PMRCAP_REG_WDS_MASK (0x1)
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#define NVME_PMRCAP_REG_BIR_SHIFT (5)
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#define NVME_PMRCAP_REG_BIR_MASK (0x7)
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#define NVME_PMRCAP_REG_PMRTU_SHIFT (8)
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#define NVME_PMRCAP_REG_PMRTU_MASK (0x3)
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#define NVME_PMRCAP_REG_PMRWBM_SHIFT (10)
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#define NVME_PMRCAP_REG_PMRWBM_MASK (0xf)
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#define NVME_PMRCAP_REG_PMRTO_SHIFT (16)
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#define NVME_PMRCAP_REG_PMRTO_MASK (0xff)
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#define NVME_PMRCAP_REG_CMSS_SHIFT (24)
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#define NVME_PMRCAP_REG_CMSS_MASK (0x1)
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#define NVME_PMRCAP_RDS(x) \
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(((x) >> NVME_PMRCAP_REG_RDS_SHIFT) & NVME_PMRCAP_REG_RDS_MASK)
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#define NVME_PMRCAP_WDS(x) \
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(((x) >> NVME_PMRCAP_REG_WDS_SHIFT) & NVME_PMRCAP_REG_WDS_MASK)
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#define NVME_PMRCAP_BIR(x) \
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(((x) >> NVME_PMRCAP_REG_BIR_SHIFT) & NVME_PMRCAP_REG_BIR_MASK)
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#define NVME_PMRCAP_PMRTU(x) \
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(((x) >> NVME_PMRCAP_REG_PMRTU_SHIFT) & NVME_PMRCAP_REG_PMRTU_MASK)
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#define NVME_PMRCAP_PMRWBM(x) \
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(((x) >> NVME_PMRCAP_REG_PMRWBM_SHIFT) & NVME_PMRCAP_REG_PMRWBM_MASK)
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#define NVME_PMRCAP_PMRTO(x) \
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(((x) >> NVME_PMRCAP_REG_PMRTO_SHIFT) & NVME_PMRCAP_REG_PMRTO_MASK)
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#define NVME_PMRCAP_CMSS(x) \
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(((x) >> NVME_PMRCAP_REG_CMSS_SHIFT) & NVME_PMRCAP_REG_CMSS_MASK)
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/* Command field definitions */
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#define NVME_CMD_FUSE_SHIFT (8)
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@ -1367,7 +1367,7 @@ nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev)
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struct make_dev_args md_args;
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uint32_t cap_lo;
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uint32_t cap_hi;
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uint32_t to, vs;
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uint32_t to, vs, pmrcap;
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uint8_t mpsmin;
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int status, timeout_period;
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@ -1390,21 +1390,33 @@ nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev)
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cap_hi = nvme_mmio_read_4(ctrlr, cap_hi);
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if (bootverbose) {
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device_printf(dev, "CapHi: 0x%08x: DSTRD %u%s, CSS %x%s, "
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"MPSMIN %u, MPSMAX %u %s%s\n", cap_hi,
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"MPSMIN %u, MPSMAX %u%s%s\n", cap_hi,
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NVME_CAP_HI_DSTRD(cap_hi),
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NVME_CAP_HI_NSSRS(cap_lo) ? ", NSSRS" : "",
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NVME_CAP_HI_NSSRS(cap_hi) ? ", NSSRS" : "",
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NVME_CAP_HI_CSS(cap_hi),
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NVME_CAP_HI_BPS(cap_lo) ? ", BPS" : "",
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NVME_CAP_HI_BPS(cap_hi) ? ", BPS" : "",
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NVME_CAP_HI_MPSMIN(cap_hi),
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NVME_CAP_HI_MPSMAX(cap_hi),
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NVME_CAP_HI_PMRS(cap_lo) ? ", PMRS" : "",
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NVME_CAP_HI_CMBS(cap_lo) ? ", CMBS" : "");
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NVME_CAP_HI_PMRS(cap_hi) ? ", PMRS" : "",
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NVME_CAP_HI_CMBS(cap_hi) ? ", CMBS" : "");
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}
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if (bootverbose) {
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vs = nvme_mmio_read_4(ctrlr, vs);
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device_printf(dev, "Version: 0x%08x: %d.%d\n", vs,
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NVME_MAJOR(vs), NVME_MINOR(vs));
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}
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if (bootverbose && NVME_CAP_HI_PMRS(cap_hi)) {
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pmrcap = nvme_mmio_read_4(ctrlr, pmrcap);
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device_printf(dev, "PMRCap: 0x%08x: BIR %u%s%s, PMRTU %u, "
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"PMRWBM %x, PMRTO %u%s\n", pmrcap,
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NVME_PMRCAP_BIR(pmrcap),
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NVME_PMRCAP_RDS(pmrcap) ? ", RDS" : "",
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NVME_PMRCAP_WDS(pmrcap) ? ", WDS" : "",
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NVME_PMRCAP_PMRTU(pmrcap),
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NVME_PMRCAP_PMRWBM(pmrcap),
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NVME_PMRCAP_PMRTO(pmrcap),
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NVME_PMRCAP_CMSS(pmrcap) ? ", CMSS" : "");
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}
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ctrlr->dstrd = NVME_CAP_HI_DSTRD(cap_hi) + 2;
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