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Pull in r263301 from upstream llvm trunk (by Ahmed Bougacha):
[AArch64] Don't blindly lower f16/f128 FCCMPs. Instead, extend f16 (like we do when lowering a standalone SETCC), and let f128 be legalized to the RT calls. Fixes PR26803. This fixes a fatal "Cannot select" backend error when building the net/freerdp port for AArch64. PR: 214380 MFC after: 3 days
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=308487
@ -1177,8 +1177,14 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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SDLoc dl, SelectionDAG &DAG) {
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EVT VT = LHS.getValueType();
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if (VT.isFloatingPoint())
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if (VT.isFloatingPoint()) {
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assert(VT != MVT::f128);
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if (VT == MVT::f16) {
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LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
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RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
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}
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return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
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}
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// The CMP instruction is just an alias for SUBS, and representing it as
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// SUBS means that it's possible to get CSE with subtract operations.
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@ -1261,9 +1267,14 @@ static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
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SDValue Condition, unsigned NZCV,
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SDLoc DL, SelectionDAG &DAG) {
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unsigned Opcode = 0;
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if (LHS.getValueType().isFloatingPoint())
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if (LHS.getValueType().isFloatingPoint()) {
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assert(LHS.getValueType() != MVT::f128);
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if (LHS.getValueType() == MVT::f16) {
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LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS);
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RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS);
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}
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Opcode = AArch64ISD::FCCMP;
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else if (RHS.getOpcode() == ISD::SUB) {
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} else if (RHS.getOpcode() == ISD::SUB) {
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SDValue SubOp0 = RHS.getOperand(0);
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if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
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// See emitComparison() on why we can only do this for SETEQ and SETNE.
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@ -1290,6 +1301,8 @@ static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanPushNegate,
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return false;
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unsigned Opcode = Val->getOpcode();
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if (Opcode == ISD::SETCC) {
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if (Val->getOperand(0).getValueType() == MVT::f128)
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return false;
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CanPushNegate = true;
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return true;
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}
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