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Add the actual source too :)

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Approved by:	re
This commit is contained in:
Jack F Vogel 2007-07-11 23:03:16 +00:00
parent c27bff78be
commit 13705f88fa
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=171384
12 changed files with 9206 additions and 0 deletions
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$FreeBSD$
Copyright (c) 2001-2007, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

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sys/dev/ixgbe/ixgbe.c Normal file
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sys/dev/ixgbe/ixgbe.h Normal file
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/**************************************************************************
Copyright (c) 2001-2007, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
***************************************************************************/
/* $FreeBSD$ */
#ifndef _IXGBE_H_
#define _IXGBE_H_
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/mbuf.h>
#include <sys/protosw.h>
#include <sys/socket.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/sockio.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/bpf.h>
#include <net/ethernet.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/bpf.h>
#include <net/if_types.h>
#include <net/if_vlan_var.h>
#include <netinet/in_systm.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
#include <netinet/ip.h>
#include <netinet/ip6.h>
#include <netinet/tcp.h>
#include <netinet/udp.h>
#include <machine/in_cksum.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/clock.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <sys/proc.h>
#include <sys/sysctl.h>
#include <sys/endian.h>
#include <sys/taskqueue.h>
#include "ixgbe_api.h"
/* Tunables */
/*
** The number of queues: right now significant performance
** seems to be gained by using muliple RX queues. The
** infrastructure for multiple TX is there but its not
** completely working, dont set greater than 1 for now.
** OTHER is the vector used for link changes, it also
** should only be set to 1.
*/
#define IXGBE_TX_QUEUES 1
#define IXGBE_RX_QUEUES 8
#define IXGBE_OTHER 1
/*
* TxDescriptors Valid Range: 64-4096 Default Value: 2048 This value is the
* number of transmit descriptors allocated by the driver. Increasing this
* value allows the driver to queue more transmits. Each descriptor is 16
* bytes.
*/
#define DEFAULT_TXD 2048
#define MAX_TXD 4096
#define MIN_TXD 64
/*
* RxDescriptors Valid Range: 64-4096 Default Value: 2048 This value is the
* number of receive descriptors allocated by the driver. Increasing this
* value allows the driver to buffer more incoming packets. Each descriptor
* is 16 bytes. A receive buffer is also allocated for each descriptor. The
* maximum MTU size is 16110.
*
*/
#define DEFAULT_RXD 2048
#define MAX_RXD 4096
#define MIN_RXD 64
/*
* This parameter controls the maximum no of times the driver will loop in
* the isr. Minimum Value = 1
*/
#define MAX_INTR 10
/*
* This parameter controls the duration of transmit watchdog timer.
*/
#define IXGBE_TX_TIMEOUT 5 /* set to 5 seconds */
/*
* This parameters control when the driver calls the routine to reclaim
* transmit descriptors.
*/
#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
#define IXGBE_MAX_FRAME_SIZE 0x3F00
#define PERFORMANCE_MTU 9000 /* Best thruput results */
/*
** This controls the size mbuf pool used, it
** may ultimately be automatic, but for now its
** a compile time option.
** - use MCLBYTES for legacy size
*/
#define IXGBE_RXBUF MJUMPAGESIZE
/* Defines for printing debug information */
#define DEBUG_INIT 0
#define DEBUG_IOCTL 0
#define DEBUG_HW 0
#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
#define MAX_NUM_MULTICAST_ADDRESSES 128
#define IXGBE_MAX_SCATTER 100
#define IXGBE_MMBA 0x0010
#define IXGBE_TSO_SIZE 65535
#define IXGBE_TX_BUFFER_SIZE ((u32) 1514)
#define IXGBE_RX_HDR_SIZE ((u32) 256)
#define CSUM_OFFLOAD 7 /* Bits in csum flags */
/* The number of MSIX messages the 82598 supports */
#define IXGBE_MSGS 18
/*
* Interrupt Moderation parameters
* for now we hardcode, later
* it would be nice to do dynamic
*/
#define DEFAULT_ITR 8000
#define LINK_ITR 1950
/*
* ******************************************************************************
* vendor_info_array
*
* This array contains the list of Subvendor/Subdevice IDs on which the driver
* should load.
*
*****************************************************************************
*/
typedef struct _ixgbe_vendor_info_t {
unsigned int vendor_id;
unsigned int device_id;
unsigned int subvendor_id;
unsigned int subdevice_id;
unsigned int index;
} ixgbe_vendor_info_t;
struct ixgbe_tx_buf {
int next_eop;
struct mbuf *m_head;
bus_dmamap_t map;
};
struct ixgbe_rx_buf {
struct mbuf *m_head;
boolean_t bigbuf;
/* one small and one large map */
bus_dmamap_t map[2];
};
/*
* Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free.
*/
struct ixgbe_dma_alloc {
bus_addr_t dma_paddr;
caddr_t dma_vaddr;
bus_dma_tag_t dma_tag;
bus_dmamap_t dma_map;
bus_dma_segment_t dma_seg;
bus_size_t dma_size;
int dma_nseg;
};
/*
* The transmit ring, one per tx queue
*/
struct tx_ring {
struct adapter *adapter;
u32 me;
struct mtx mtx;
union ixgbe_adv_tx_desc *tx_base;
struct ixgbe_dma_alloc txdma;
uint32_t next_avail_tx_desc;
uint32_t next_tx_to_clean;
struct ixgbe_tx_buf *tx_buffers;
volatile uint16_t tx_avail;
uint32_t txd_cmd;
bus_dma_tag_t txtag;
};
/*
* The Receive ring, one per rx queue
*/
struct rx_ring {
struct adapter *adapter;
u32 me;
struct mtx mtx;
u32 payload;
union ixgbe_adv_rx_desc *rx_base;
struct ixgbe_dma_alloc rxdma;
unsigned int last_cleaned;
unsigned int next_to_check;
struct ixgbe_rx_buf *rx_buffers;
bus_dma_tag_t rxtag[2];
bus_dmamap_t spare_map[2];
struct mbuf *fmp;
struct mbuf *lmp;
/* Soft stats */
u64 packet_count;
u64 byte_count;
};
/* Our adapter structure */
struct adapter {
struct ifnet *ifp;
struct ixgbe_hw hw;
/* FreeBSD operating-system-specific structures */
struct ixgbe_osdep osdep;
struct device *dev;
struct resource *res_memory;
struct resource *res_msix;
/*
* Interrupt resources:
* Oplin has 20 MSIX messages
* so allocate that for now.
*/
void *tag[IXGBE_MSGS];
struct resource *res[IXGBE_MSGS];
int rid[IXGBE_MSGS];
struct ifmedia media;
struct callout timer;
int watchdog_timer;
int msix;
int if_flags;
struct mtx mtx;
/* Info about the board itself */
uint32_t part_num;
boolean_t link_active;
uint16_t max_frame_size;
uint16_t link_duplex;
uint32_t tx_int_delay;
uint32_t tx_abs_int_delay;
uint32_t rx_int_delay;
uint32_t rx_abs_int_delay;
/* Indicates the cluster size to use */
boolean_t bigbufs;
/*
* Transmit rings:
* Allocated at run time, an array of rings.
*/
struct tx_ring *tx_rings;
int num_tx_desc;
int num_tx_queues;
/*
* Receive rings:
* Allocated at run time, an array of rings.
*/
struct rx_ring *rx_rings;
int num_rx_desc;
int num_rx_queues;
uint32_t rx_process_limit;
/* Misc stats maintained by the driver */
unsigned long dropped_pkts;
unsigned long mbuf_alloc_failed;
unsigned long mbuf_cluster_failed;
unsigned long no_tx_desc_avail1;
unsigned long no_tx_desc_avail2;
unsigned long no_tx_map_avail;
unsigned long no_tx_dma_setup;
unsigned long watchdog_events;
unsigned long tso_tx;
struct ixgbe_hw_stats stats;
};
#define IXGBE_LOCK_INIT(_sc, _name) \
mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
#define IXGBE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
#define IXGBE_LOCK(_sc) mtx_lock(&(_sc)->mtx)
#define IXGBE_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
#define IXGBE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
#endif /* _IXGBE_H_ */

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sys/dev/ixgbe/ixgbe_82598.c Normal file
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/*******************************************************************************
Copyright (c) 2001-2007, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* $FreeBSD$ */
#include "ixgbe_type.h"
#include "ixgbe_api.h"
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
#define IXGBE_82598_MAX_TX_QUEUES 32
#define IXGBE_82598_MAX_RX_QUEUES 64
#define IXGBE_82598_RAR_ENTRIES 16
s32 ixgbe_init_shared_code_82598(struct ixgbe_hw *hw);
s32 ixgbe_assign_func_pointers_82598(struct ixgbe_hw *hw);
s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
bool *autoneg);
s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
bool *autoneg);
enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
u32 ixgbe_get_num_of_tx_queues_82598(struct ixgbe_hw *hw);
u32 ixgbe_get_num_of_rx_queues_82598(struct ixgbe_hw *hw);
s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
bool *link_up);
s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
bool autoneg,
bool autoneg_wait_to_complete);
s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
s32 ixgbe_check_copper_link_82598(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
bool *link_up);
s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
bool autoneg,
bool autoneg_wait_to_complete);
#ifndef NO_82598_A0_SUPPORT
s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw);
#endif
s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
u32 ixgbe_get_num_rx_addrs_82598(struct ixgbe_hw *hw);
/**
* ixgbe_init_shared_code_82598 - Inits func ptrs and MAC type
* @hw: pointer to hardware structure
*
* Initialize the shared code for 82598. This will assign function pointers
* and assign the MAC type. Does not touch the hardware.
**/
s32 ixgbe_init_shared_code_82598(struct ixgbe_hw *hw)
{
/* Set MAC type */
hw->mac.type = ixgbe_mac_82598EB;
/* Assign function pointers */
ixgbe_assign_func_pointers_82598(hw);
return IXGBE_SUCCESS;
}
/**
* ixgbe_assign_func_pointers_82598 - Assigns 82598-specific funtion pointers
* @hw: pointer to hardware structure
*
* Note - Generic function pointers have already been assigned, so the
* function pointers set here are only for 82598-specific functions.
**/
s32 ixgbe_assign_func_pointers_82598(struct ixgbe_hw *hw)
{
hw->func.ixgbe_func_get_media_type =
&ixgbe_get_media_type_82598;
hw->func.ixgbe_func_get_num_of_tx_queues =
&ixgbe_get_num_of_tx_queues_82598;
hw->func.ixgbe_func_get_num_of_rx_queues =
&ixgbe_get_num_of_rx_queues_82598;
#ifndef NO_82598_A0_SUPPORT
if (hw->revision_id == 0) {
hw->func.ixgbe_func_reset_hw =
&ixgbe_reset_hw_rev_0_82598;
} else {
hw->func.ixgbe_func_reset_hw = &ixgbe_reset_hw_82598;
}
#else
hw->func.ixgbe_func_reset_hw = &ixgbe_reset_hw_82598;
#endif
hw->func.ixgbe_func_get_num_rx_addrs =
&ixgbe_get_num_rx_addrs_82598;
/* Link */
if (ixgbe_get_media_type(hw) == ixgbe_media_type_copper) {
hw->func.ixgbe_func_setup_link =
&ixgbe_setup_copper_link_82598;
hw->func.ixgbe_func_check_link =
&ixgbe_check_copper_link_82598;
hw->func.ixgbe_func_setup_link_speed =
&ixgbe_setup_copper_link_speed_82598;
hw->func.ixgbe_func_get_link_settings =
&ixgbe_get_copper_link_settings_82598;
} else {
hw->func.ixgbe_func_setup_link =
&ixgbe_setup_mac_link_82598;
hw->func.ixgbe_func_check_link =
&ixgbe_check_mac_link_82598;
hw->func.ixgbe_func_setup_link_speed =
&ixgbe_setup_mac_link_speed_82598;
hw->func.ixgbe_func_get_link_settings =
&ixgbe_get_link_settings_82598;
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_get_link_settings_82598 - Determines default link settings
* @hw: pointer to hardware structure
* @speed: pointer to link speed
* @autoneg: boolean auto-negotiation value
*
* Determines the default link settings by reading the AUTOC register.
**/
s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *autoneg)
{
s32 status = IXGBE_SUCCESS;
s32 autoc_reg;
autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
if (hw->mac.link_settings_loaded) {
autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
autoc_reg |= hw->mac.link_attach_type;
autoc_reg |= hw->mac.link_mode_select;
}
switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) {
case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
*speed = IXGBE_LINK_SPEED_1GB_FULL;
*autoneg = FALSE;
break;
case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
*speed = IXGBE_LINK_SPEED_10GB_FULL;
*autoneg = FALSE;
break;
case IXGBE_AUTOC_LMS_1G_AN:
*speed = IXGBE_LINK_SPEED_1GB_FULL;
*autoneg = TRUE;
break;
case IXGBE_AUTOC_LMS_KX4_AN:
case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
*speed = IXGBE_LINK_SPEED_UNKNOWN;
if (autoc_reg & IXGBE_AUTOC_KX4_SUPP) {
*speed |= IXGBE_LINK_SPEED_10GB_FULL;
}
if (autoc_reg & IXGBE_AUTOC_KX_SUPP) {
*speed |= IXGBE_LINK_SPEED_1GB_FULL;
}
*autoneg = TRUE;
break;
default:
status = IXGBE_ERR_LINK_SETUP;
break;
}
return status;
}
/**
* ixgbe_get_copper_link_settings_82598 - Determines default link settings
* @hw: pointer to hardware structure
* @speed: pointer to link speed
* @autoneg: boolean auto-negotiation value
*
* Determines the default link settings by reading the AUTOC register.
**/
s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
bool *autoneg)
{
s32 status = IXGBE_ERR_LINK_SETUP;
u16 speed_ability;
*speed = 0;
*autoneg = TRUE;
status = ixgbe_read_phy_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
IXGBE_MDIO_PMA_PMD_DEV_TYPE,
&speed_ability);
if (status == IXGBE_SUCCESS) {
if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
*speed |= IXGBE_LINK_SPEED_10GB_FULL;
if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
*speed |= IXGBE_LINK_SPEED_1GB_FULL;
}
return status;
}
/**
* ixgbe_get_media_type_82598 - Determines media type
* @hw: pointer to hardware structure
*
* Returns the media type (fiber, copper, backplane)
**/
enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
{
enum ixgbe_media_type media_type;
/* Media type for I82598 is based on device ID */
switch (hw->device_id) {
case IXGBE_DEV_ID_82598:
/* Default device ID is mezzanine card KX/KX4 */
media_type = ixgbe_media_type_backplane;
break;
case IXGBE_DEV_ID_82598_FPGA:
case IXGBE_DEV_ID_82598AF_DUAL_PORT:
case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
media_type = ixgbe_media_type_fiber;
break;
case IXGBE_DEV_ID_82598AT_DUAL_PORT:
media_type = ixgbe_media_type_copper;
break;
default:
media_type = ixgbe_media_type_unknown;
break;
}
return media_type;
}
/**
* ixgbe_get_num_of_tx_queues_82598 - Get number of TX queues
* @hw: pointer to hardware structure
*
* Returns the number of transmit queues for the given adapter.
**/
u32 ixgbe_get_num_of_tx_queues_82598(struct ixgbe_hw *hw)
{
if (hw->device_id == IXGBE_DEV_ID_82598_FPGA)
return 8;
return IXGBE_82598_MAX_TX_QUEUES;
}
/**
* ixgbe_get_num_of_rx_queues_82598 - Get number of RX queues
* @hw: pointer to hardware structure
*
* Returns the number of receive queues for the given adapter.
**/
u32 ixgbe_get_num_of_rx_queues_82598(struct ixgbe_hw *hw)
{
if (hw->device_id == IXGBE_DEV_ID_82598_FPGA)
return 8;
return IXGBE_82598_MAX_RX_QUEUES;
}
/**
* ixgbe_setup_mac_link_82598 - Configures MAC link settings
* @hw: pointer to hardware structure
*
* Configures link settings based on values in the ixgbe_hw struct.
* Restarts the link. Performs autonegotiation if needed.
**/
s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
{
u32 autoc_reg;
u32 links_reg;
u32 i;
s32 status = IXGBE_SUCCESS;
autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
if (hw->mac.link_settings_loaded) {
autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
autoc_reg |= hw->mac.link_attach_type;
autoc_reg |= hw->mac.link_mode_select;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
msec_delay(50);
}
/* Restart link */
autoc_reg |= IXGBE_AUTOC_AN_RESTART;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
/* Only poll for autoneg to complete if specified to do so */
if (hw->phy.autoneg_wait_to_complete) {
if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN ||
hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
links_reg = 0; /* Just in case Autoneg time = 0 */
for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
if (links_reg & IXGBE_LINKS_KX_AN_COMP)
break;
msec_delay(100);
}
if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
DEBUGOUT("Autonegotiation did not complete.\n");
}
}
}
/* Add delay to filter out noises during initial link setup */
msec_delay(50);
return status;
}
/**
* ixgbe_check_mac_link_82598 - Get link/speed status
* @hw: pointer to hardware structure
* @speed: pointer to link speed
* @link_up: TRUE is link is up, FALSE otherwise
*
* Reads the links register to determine if link is up and the current speed
**/
s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *link_up)
{
u32 links_reg;
links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
if (links_reg & IXGBE_LINKS_UP)
*link_up = TRUE;
else
*link_up = FALSE;
if (links_reg & IXGBE_LINKS_SPEED)
*speed = IXGBE_LINK_SPEED_10GB_FULL;
else
*speed = IXGBE_LINK_SPEED_1GB_FULL;
return IXGBE_SUCCESS;
}
/**
* ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: TRUE if auto-negotiation enabled
* @autoneg_wait_to_complete: TRUE if waiting is needed to complete
*
* Set the link speed in the AUTOC register and restarts link.
**/
s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
ixgbe_link_speed speed, bool autoneg,
bool autoneg_wait_to_complete)
{
s32 status = IXGBE_SUCCESS;
/* If speed is 10G, then check for CX4 or XAUI. */
if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
(!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4)))
hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg))
hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
else if (autoneg) {
/* BX mode - Autonegotiate 1G */
if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD))
hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN;
else /* KX/KX4 mode */
hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN;
} else {
status = IXGBE_ERR_LINK_SETUP;
}
if (status == IXGBE_SUCCESS) {
hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
hw->mac.link_settings_loaded = TRUE;
/*
* Setup and restart the link based on the new values in
* ixgbe_hw This will write the AUTOC register based on the new
* stored values
*/
ixgbe_setup_mac_link_82598(hw);
}
return status;
}
/**
* ixgbe_setup_copper_link_82598 - Setup copper link settings
* @hw: pointer to hardware structure
*
* Configures link settings based on values in the ixgbe_hw struct.
* Restarts the link. Performs autonegotiation if needed. Restart
* phy and wait for autonegotiate to finish. Then synchronize the
* MAC and PHY.
**/
s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
{
s32 status;
ixgbe_link_speed speed = 0;
bool link_up = FALSE;
/* Set up MAC */
ixgbe_setup_mac_link_82598(hw);
/* Restart autonegotiation on PHY */
status = ixgbe_setup_phy_link(hw);
/* Synchronize MAC to PHY speed */
if (status == IXGBE_SUCCESS)
status = ixgbe_check_link(hw, &speed, &link_up);
return status;
}
/**
* ixgbe_check_copper_link_82598 - Syncs MAC & PHY link settings
* @hw: pointer to hardware structure
* @speed: pointer to link speed
* @link_up: TRUE if link is up, FALSE otherwise
*
* Reads the mac link, phy link, and synchronizes the MAC to PHY.
**/
s32 ixgbe_check_copper_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *link_up)
{
s32 status;
ixgbe_link_speed phy_speed = 0;
bool phy_link = FALSE;
/* This is the speed and link the MAC is set at */
ixgbe_check_mac_link_82598(hw, speed, link_up);
/*
* Check current speed and link status of the PHY register.
* This is a vendor specific register and may have to
* be changed for other copper PHYs.
*/
status = ixgbe_check_phy_link(hw, &phy_speed, &phy_link);
if ((status == IXGBE_SUCCESS) && (phy_link)) {
/*
* Check current link status of the MACs link's register
* matches that of the speed in the PHY register
*/
if (*speed != phy_speed) {
/*
* The copper PHY requires 82598 attach type to be XAUI
* for 10G and BX for 1G
*/
hw->mac.link_attach_type =
(IXGBE_AUTOC_10G_XAUI | IXGBE_AUTOC_1G_BX);
/* Synchronize the MAC speed to the PHY speed */
status = ixgbe_setup_mac_link_speed_82598(hw, phy_speed,
FALSE, FALSE);
if (status == IXGBE_SUCCESS)
ixgbe_check_mac_link_82598(hw, speed, link_up);
else
status = IXGBE_ERR_LINK_SETUP;
}
} else {
*link_up = phy_link;
}
return status;
}
/**
* ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: TRUE if autonegotiation enabled
* @autoneg_wait_to_complete: TRUE if waiting is needed to complete
*
* Sets the link speed in the AUTOC register in the MAC and restarts link.
**/
s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
bool autoneg,
bool autoneg_wait_to_complete)
{
s32 status;
bool link_up = 0;
/* Setup the PHY according to input speed */
status = ixgbe_setup_phy_link_speed(hw, speed, autoneg,
autoneg_wait_to_complete);
/* Synchronize MAC to PHY speed */
if (status == IXGBE_SUCCESS)
status = ixgbe_check_link(hw, &speed, &link_up);
return status;
}
#ifndef NO_82598_A0_SUPPORT
/**
* ixgbe_reset_hw_rev_0_82598 - Performs hardware reset
* @hw: pointer to hardware structure
*
* Resets the hardware by reseting the transmit and receive units, masks and
* clears all interrupts, performing a PHY reset, and performing a link (MAC)
* reset.
**/
s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
u32 ctrl;
u32 gheccr;
u32 autoc;
u32 i;
u32 resets;
/* Call adapter stop to disable tx/rx and clear interrupts */
ixgbe_stop_adapter(hw);
/* Reset PHY */
ixgbe_reset_phy(hw);
for (resets = 0; resets < 10; resets++) {
/*
* Prevent the PCI-E bus from from hanging by disabling PCI-E
* master access and verify no pending requests before reset
*/
if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) {
status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
DEBUGOUT("PCI-E Master disable polling has failed.\n");
}
/*
* Issue global reset to the MAC. This needs to be a SW reset.
* If link reset is used, it might reset the MAC when mng is
* using it.
*/
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
IXGBE_WRITE_FLUSH(hw);
/*
* Poll for reset bit to self-clear indicating reset is
* complete
*/
for (i = 0; i < 10; i++) {
usec_delay(1);
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
if (!(ctrl & IXGBE_CTRL_RST))
break;
}
if (ctrl & IXGBE_CTRL_RST) {
status = IXGBE_ERR_RESET_FAILED;
DEBUGOUT("Reset polling failed to complete.\n");
}
}
msec_delay(50);
gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
/*
* AUTOC register which stores link settings gets cleared
* and reloaded from EEPROM after reset. We need to restore
* our stored value from init in case SW changed the attach
* type or speed. If this is the first time and link settings
* have not been stored, store default settings from AUTOC.
*/
autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
if (hw->mac.link_settings_loaded) {
autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE);
autoc &= ~(IXGBE_AUTOC_LMS_MASK);
autoc |= hw->mac.link_attach_type;
autoc |= hw->mac.link_mode_select;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
} else {
hw->mac.link_attach_type =
(autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
hw->mac.link_settings_loaded = TRUE;
}
/* Store the permanent mac address */
ixgbe_get_mac_addr(hw, hw->mac.perm_addr);
return status;
}
#endif /* NO_A0_SUPPORT */
/**
* ixgbe_reset_hw_82598 - Performs hardware reset
* @hw: pointer to hardware structure
*
* Resets the hardware by reseting the transmit and receive units, masks and
* clears all interrupts, performing a PHY reset, and performing a link (MAC)
* reset.
**/
s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
u32 ctrl;
u32 gheccr;
u32 i;
u32 autoc;
/* Call adapter stop to disable tx/rx and clear interrupts */
ixgbe_stop_adapter(hw);
/* Reset PHY */
ixgbe_reset_phy(hw);
/*
* Prevent the PCI-E bus from from hanging by disabling PCI-E master
* access and verify no pending requests before reset
*/
if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) {
status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
DEBUGOUT("PCI-E Master disable polling has failed.\n");
}
/*
* Issue global reset to the MAC. This needs to be a SW reset.
* If link reset is used, it might reset the MAC when mng is using it
*/
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
IXGBE_WRITE_FLUSH(hw);
/* Poll for reset bit to self-clear indicating reset is complete */
for (i = 0; i < 10; i++) {
usec_delay(1);
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
if (!(ctrl & IXGBE_CTRL_RST))
break;
}
if (ctrl & IXGBE_CTRL_RST) {
status = IXGBE_ERR_RESET_FAILED;
DEBUGOUT("Reset polling failed to complete.\n");
}
msec_delay(50);
gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
/*
* AUTOC register which stores link settings gets cleared
* and reloaded from EEPROM after reset. We need to restore
* our stored value from init in case SW changed the attach
* type or speed. If this is the first time and link settings
* have not been stored, store default settings from AUTOC.
*/
autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
if (hw->mac.link_settings_loaded) {
autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE);
autoc &= ~(IXGBE_AUTOC_LMS_MASK);
autoc |= hw->mac.link_attach_type;
autoc |= hw->mac.link_mode_select;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
} else {
hw->mac.link_attach_type =
(autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
hw->mac.link_settings_loaded = TRUE;
}
/* Store the permanent mac address */
ixgbe_get_mac_addr(hw, hw->mac.perm_addr);
return status;
}
/**
* ixgbe_get_num_rx_addrs_82598 - Get RX address registers
* @hw: pointer to hardware structure
*
* Returns the of RAR entries for the given adapter.
**/
u32 ixgbe_get_num_rx_addrs_82598(struct ixgbe_hw *hw)
{
UNREFERENCED_PARAMETER(hw);
return IXGBE_82598_RAR_ENTRIES;
}

645
sys/dev/ixgbe/ixgbe_api.c Normal file
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@ -0,0 +1,645 @@
/*******************************************************************************
Copyright (c) 2001-2007, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* $FreeBSD$ */
#include "ixgbe_api.h"
#include "ixgbe_common.h"
extern s32 ixgbe_init_shared_code_82598(struct ixgbe_hw *hw);
extern s32 ixgbe_init_shared_code_phy(struct ixgbe_hw *hw);
/**
* ixgbe_init_shared_code - Initialize the shared code
* @hw: pointer to hardware structure
*
* This will assign function pointers and assign the MAC type and PHY code.
* Does not touch the hardware. This function must be called prior to any
* other function in the shared code. The ixgbe_hw structure should be
* memset to 0 prior to calling this function. The following fields in
* hw structure should be filled in prior to calling this function:
* hw_addr, back, device_id, vendor_id, subsystem_device_id,
* subsystem_vendor_id, and revision_id
**/
s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
{
s32 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
/*
* Assign generic function pointers before entering adapter-specific
* init
*/
ixgbe_assign_func_pointers_generic(hw);
if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
switch (hw->device_id) {
case IXGBE_DEV_ID_82598:
case IXGBE_DEV_ID_82598_FPGA:
case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
case IXGBE_DEV_ID_82598AF_DUAL_PORT:
case IXGBE_DEV_ID_82598AT_DUAL_PORT:
status = ixgbe_init_shared_code_82598(hw);
status = ixgbe_init_shared_code_phy(hw);
break;
default:
status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
break;
}
}
return status;
}
/**
* ixgbe_init_hw - Initialize the hardware
* @hw: pointer to hardware structure
*
* Initialize the hardware by resetting and then starting the hardware
**/
s32 ixgbe_init_hw(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_init_hw, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_reset_hw - Performs a hardware reset
* @hw: pointer to hardware structure
*
* Resets the hardware by resetting the transmit and receive units, masks and
* clears all interrupts, performs a PHY reset, and performs a MAC reset
**/
s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_reset_hw, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_start_hw - Prepares hardware for TX/TX
* @hw: pointer to hardware structure
*
* Starts the hardware by filling the bus info structure and media type,
* clears all on chip counters, initializes receive address registers,
* multicast table, VLAN filter table, calls routine to setup link and
* flow control settings, and leaves transmit and receive units disabled
* and uninitialized.
**/
s32 ixgbe_start_hw(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_start_hw, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_clear_hw_cntrs - Clear hardware counters
* @hw: pointer to hardware structure
*
* Clears all hardware statistics counters by reading them from the hardware
* Statistics counters are clear on read.
**/
s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_clear_hw_cntrs, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_get_media_type - Get media type
* @hw: pointer to hardware structure
*
* Returns the media type (fiber, copper, backplane)
**/
enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_get_media_type, (hw),
ixgbe_media_type_unknown);
}
/**
* ixgbe_get_mac_addr - Get MAC address
* @hw: pointer to hardware structure
* @mac_addr: Adapter MAC address
*
* Reads the adapter's MAC address from the first Receive Address Register
* (RAR0) A reset of the adapter must have been performed prior to calling this
* function in order for the MAC address to have been loaded from the EEPROM
* into RAR0
**/
s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
{
return ixgbe_call_func(hw, ixgbe_func_get_mac_addr,
(hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_get_bus_info - Set PCI bus info
* @hw: pointer to hardware structure
*
* Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
**/
s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_get_bus_info, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_get_num_of_tx_queues - Get TX queues
* @hw: pointer to hardware structure
*
* Returns the number of transmit queues for the given adapter.
**/
u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_get_num_of_tx_queues,
(hw), 0);
}
/**
* ixgbe_get_num_of_rx_queues - Get RX queues
* @hw: pointer to hardware structure
*
* Returns the number of receive queues for the given adapter.
**/
u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_get_num_of_rx_queues,
(hw), 0);
}
/**
* ixgbe_stop_adapter - Disable TX/TX units
* @hw: pointer to hardware structure
*
* Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
* disables transmit and receive units. The adapter_stopped flag is used by
* the shared code and drivers to determine if the adapter is in a stopped
* state and should not touch the hardware.
**/
s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_stop_adapter, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_identify_phy - Get PHY type
* @hw: pointer to hardware structure
*
* Determines the physical layer module found on the current adapter.
**/
s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
if (hw->phy.type == ixgbe_phy_unknown) {
status = ixgbe_call_func(hw,
ixgbe_func_identify_phy,
(hw),
IXGBE_NOT_IMPLEMENTED);
}
return status;
}
/**
* ixgbe_reset_phy - Perform a PHY reset
* @hw: pointer to hardware structure
**/
s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
if (hw->phy.type == ixgbe_phy_unknown) {
if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) {
status = IXGBE_ERR_PHY;
}
}
if (status == IXGBE_SUCCESS) {
status = ixgbe_call_func(hw,
ixgbe_func_reset_phy,
(hw),
IXGBE_NOT_IMPLEMENTED);
}
return status;
}
/**
* ixgbe_read_phy_reg - Read PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
* @phy_data: Pointer to read data from PHY register
*
* Reads a value from a specified PHY register
**/
s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 *phy_data)
{
s32 status = IXGBE_SUCCESS;
if (hw->phy.type == ixgbe_phy_unknown) {
if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) {
status = IXGBE_ERR_PHY;
}
}
if (status == IXGBE_SUCCESS) {
status = ixgbe_call_func(hw,
ixgbe_func_read_phy_reg,
(hw, reg_addr, device_type, phy_data),
IXGBE_NOT_IMPLEMENTED);
}
return status;
}
/**
* ixgbe_write_phy_reg - Write PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
* @phy_data: Data to write to the PHY register
*
* Writes a value to specified PHY register
**/
s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 phy_data)
{
s32 status = IXGBE_SUCCESS;
if (hw->phy.type == ixgbe_phy_unknown) {
if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) {
status = IXGBE_ERR_PHY;
}
}
if (status == IXGBE_SUCCESS) {
status = ixgbe_call_func(hw,
ixgbe_func_write_phy_reg,
(hw, reg_addr, device_type, phy_data),
IXGBE_NOT_IMPLEMENTED);
}
return status;
}
/**
* ixgbe_setup_link - Configure link settings
* @hw: pointer to hardware structure
*
* Configures link settings based on values in the ixgbe_hw struct.
* Restarts the link. Performs autonegotiation if needed.
**/
s32 ixgbe_setup_link(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_setup_link, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_check_link - Get link and speed status
* @hw: pointer to hardware structure
*
* Reads the links register to determine if link is up and the current speed
**/
s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *link_up)
{
return ixgbe_call_func(hw, ixgbe_func_check_link, (hw, speed, link_up),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_setup_link_speed - Set link speed
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: TRUE if autonegotiation enabled
*
* Set the link speed and restarts the link.
**/
s32 ixgbe_setup_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
bool autoneg,
bool autoneg_wait_to_complete)
{
return ixgbe_call_func(hw, ixgbe_func_setup_link_speed, (hw, speed,
autoneg, autoneg_wait_to_complete),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_get_link_settings - Set link settings to default
* @hw: pointer to hardware structure
*
* Sets the default link settings based on attach type in the hw struct.
**/
s32 ixgbe_get_link_settings(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *autoneg)
{
return ixgbe_call_func(hw, ixgbe_func_get_link_settings, (hw, speed,
autoneg), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_led_on - Turn on LED's
* @hw: pointer to hardware structure
* @index: led number to turn on
*
* Turns on the software controllable LEDs.
**/
s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
{
return ixgbe_call_func(hw, ixgbe_func_led_on, (hw, index),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_led_off - Turn off LED's
* @hw: pointer to hardware structure
* @index: led number to turn off
*
* Turns off the software controllable LEDs.
**/
s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
{
return ixgbe_call_func(hw, ixgbe_func_led_off, (hw, index),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_blink_led_start - Blink LED's
* @hw: pointer to hardware structure
* @index: led number to blink
*
* Blink LED based on index.
**/
s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
{
return ixgbe_call_func(hw, ixgbe_func_blink_led_start, (hw, index),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_blink_led_stop - Stop blinking LED's
* @hw: pointer to hardware structure
*
* Stop blinking LED based on index.
**/
s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
{
return ixgbe_call_func(hw, ixgbe_func_blink_led_stop, (hw, index),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_init_eeprom_params - Initialiaze EEPROM parameters
* @hw: pointer to hardware structure
*
* Initializes the EEPROM parameters ixgbe_eeprom_info within the
* ixgbe_hw struct in order to set up EEPROM access.
**/
s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_init_eeprom_params, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_write_eeprom - Write word to EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be written to
* @data: 16 bit word to be written to the EEPROM
*
* Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
* called after this function, the EEPROM will most likely contain an
* invalid checksum.
**/
s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
{
s32 status;
/*
* Initialize EEPROM parameters. This will not do anything if the
* EEPROM structure has already been initialized
*/
ixgbe_init_eeprom_params(hw);
/* Check for invalid offset */
if (offset >= hw->eeprom.word_size) {
status = IXGBE_ERR_EEPROM;
} else {
status = ixgbe_call_func(hw,
ixgbe_func_write_eeprom,
(hw, offset, data),
IXGBE_NOT_IMPLEMENTED);
}
return status;
}
/**
* ixgbe_read_eeprom - Read word from EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be read
* @data: read 16 bit value from EEPROM
*
* Reads 16 bit value from EEPROM
**/
s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
{
s32 status;
/*
* Initialize EEPROM parameters. This will not do anything if the
* EEPROM structure has already been initialized
*/
ixgbe_init_eeprom_params(hw);
/* Check for invalid offset */
if (offset >= hw->eeprom.word_size) {
status = IXGBE_ERR_EEPROM;
} else {
status = ixgbe_call_func(hw,
ixgbe_func_read_eeprom,
(hw, offset, data),
IXGBE_NOT_IMPLEMENTED);
}
return status;
}
/**
* ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
* @hw: pointer to hardware structure
* @checksum_val: calculated checksum
*
* Performs checksum calculation and validates the EEPROM checksum
**/
s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
{
return ixgbe_call_func(hw, ixgbe_func_validate_eeprom_checksum,
(hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
* @hw: pointer to hardware structure
**/
s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_update_eeprom_checksum, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_set_rar - Set RX address register
* @hw: pointer to hardware structure
* @addr: Address to put into receive address register
* @index: Receive address register to write
* @vind: Vind to set RAR to
* @enable_addr: set flag that address is active
*
* Puts an ethernet address into a receive address register.
**/
s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vind,
u32 enable_addr)
{
return ixgbe_call_func(hw, ixgbe_func_set_rar, (hw, index, addr, vind,
enable_addr), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_init_rx_addrs - Initializes receive address filters.
* @hw: pointer to hardware structure
*
* Places the MAC address in receive address register 0 and clears the rest
* of the receive addresss registers. Clears the multicast table. Assumes
* the receiver is in reset when the routine is called.
**/
s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_init_rx_addrs, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
* @hw: pointer to hardware structure
**/
u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_get_num_rx_addrs, (hw), 0);
}
/**
* ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
* @hw: pointer to hardware structure
* @mc_addr_list: the list of new multicast addresses
* @mc_addr_count: number of addresses
* @pad: number of bytes between addresses in the list
*
* The given list replaces any existing list. Clears the MC addrs from receive
* address registers and the multicast table. Uses unsed receive address
* registers for the first multicast addresses, and hashes the rest into the
* multicast table.
**/
s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
u32 mc_addr_count, u32 pad)
{
return ixgbe_call_func(hw, ixgbe_func_update_mc_addr_list, (hw,
mc_addr_list, mc_addr_count, pad),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_enable_mc - Enable multicast address in RAR
* @hw: pointer to hardware structure
*
* Enables multicast address in RAR and the use of the multicast hash table.
**/
s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_enable_mc, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_disable_mc - Disable multicast address in RAR
* @hw: pointer to hardware structure
*
* Disables multicast address in RAR and the use of the multicast hash table.
**/
s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_disable_mc, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_clear_vfta - Clear VLAN filter table
* @hw: pointer to hardware structure
*
* Clears the VLAN filer table, and the VMDq index associated with the filter
**/
s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_clear_vfta, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_set_vfta - Set VLAN filter table
* @hw: pointer to hardware structure
* @vlan: VLAN id to write to VLAN filter
* @vind: VMDq output index that maps queue to VLAN id in VFTA
* @vlan_on: boolean flag to turn on/off VLAN in VFTA
*
* Turn on/off specified VLAN in the VLAN filter table.
**/
s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
{
return ixgbe_call_func(hw, ixgbe_func_set_vfta, (hw, vlan, vind,
vlan_on), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_setup_fc - Set flow control
* @hw: pointer to hardware structure
* @packetbuf_num: packet buffer number (0-7)
*
* Configures the flow control settings based on SW configuration.
**/
s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
{
return ixgbe_call_func(hw, ixgbe_func_setup_fc, (hw, packetbuf_num),
IXGBE_NOT_IMPLEMENTED);
}

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/*******************************************************************************
Copyright (c) 2001-2007, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* $FreeBSD$ */
#ifndef _IXGBE_API_H_
#define _IXGBE_API_H_
#include "ixgbe_type.h"
s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
s32 ixgbe_init_hw(struct ixgbe_hw *hw);
s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
s32 ixgbe_start_hw(struct ixgbe_hw *hw);
s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);
s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);
s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);
u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 *phy_data);
s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 phy_data);
s32 ixgbe_setup_link(struct ixgbe_hw *hw);
s32 ixgbe_setup_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
bool autoneg, bool autoneg_wait_to_complete);
s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *link_up);
s32 ixgbe_get_link_settings(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *autoneg);
s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr,
u32 vind, u32 enable_addr);
s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
u32 mc_addr_count, u32 pad);
s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
u32 vind, bool vlan_on);
s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
#endif /* _IXGBE_API_H_ */

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/*******************************************************************************
Copyright (c) 2001-2007, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* $FreeBSD$ */
#ifndef _IXGBE_COMMON_H_
#define _IXGBE_COMMON_H_
#include "ixgbe_type.h"
s32 ixgbe_assign_func_pointers_generic(struct ixgbe_hw *hw);
s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
u16 *data);
s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
u16 *checksum_val);
s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr,
u32 vind, u32 enable_addr);
s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
u32 mc_addr_count, u32 pad);
s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
u32 vind, bool vlan_on);
s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packtetbuf_num);
s32 ixgbe_validate_mac_addr(u8 *mac_addr);
s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
#endif /* IXGBE_COMMON */

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/**************************************************************************
Copyright (c) 2001-2007, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
***************************************************************************/
/* $FreeBSD$ */
#ifndef _IXGBE_OS_H_
#define _IXGBE_OS_H_
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/mbuf.h>
#include <sys/protosw.h>
#include <sys/socket.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/clock.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#define ASSERT(x) if(!(x)) panic("IXGBE: x")
/* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */
#define usec_delay(x) DELAY(x)
#define msec_delay(x) DELAY(1000*(x))
#define DBG 0
#define MSGOUT(S, A, B) printf(S "\n", A, B)
#define DEBUGFUNC(F) DEBUGOUT(F);
#if DBG
#define DEBUGOUT(S) printf(S "\n")
#define DEBUGOUT1(S,A) printf(S "\n",A)
#define DEBUGOUT2(S,A,B) printf(S "\n",A,B)
#define DEBUGOUT3(S,A,B,C) printf(S "\n",A,B,C)
#define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S "\n",A,B,C,D,E,F,G)
#else
#define DEBUGOUT(S)
#define DEBUGOUT1(S,A)
#define DEBUGOUT2(S,A,B)
#define DEBUGOUT3(S,A,B,C)
#define DEBUGOUT6(S,A,B,C,D,E,F)
#define DEBUGOUT7(S,A,B,C,D,E,F,G)
#endif
#define FALSE 0
#define TRUE 1
#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
#define PCI_COMMAND_REGISTER PCIR_COMMAND
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef int32_t s32;
typedef uint64_t u64;
typedef booleant bool;
#define le16_to_cpu
struct ixgbe_osdep
{
bus_space_tag_t mem_bus_space_tag;
bus_space_handle_t mem_bus_space_handle;
struct device *dev;
};
/* This is needed by the shared code */
struct ixgbe_hw;
extern u16 ixgbe_read_pci_cfg(struct ixgbe_hw *, u32);
#define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg
#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
#define IXGBE_READ_REG(a, reg) (\
bus_space_read_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
reg))
#define IXGBE_WRITE_REG(a, reg, value) (\
bus_space_write_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
reg, value))
#define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
bus_space_read_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
(reg + ((offset) << 2))))
#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
bus_space_write_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
(reg + ((offset) << 2)), value))
#endif /* _IXGBE_OS_H_ */

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/*******************************************************************************
Copyright (c) 2001-2007, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* $FreeBSD$ */
#include "ixgbe_api.h"
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
/**
* ixgbe_init_shared_code_phy - Initialize PHY shared code
* @hw: pointer to hardware structure
**/
s32 ixgbe_init_shared_code_phy(struct ixgbe_hw *hw)
{
/* Assign function pointers */
ixgbe_assign_func_pointers_phy(hw);
return IXGBE_SUCCESS;
}
/**
* ixgbe_assign_func_pointers_phy - Assigns PHY-specific function pointers
* @hw: pointer to hardware structure
*
* Note, generic function pointers have already been assigned, so the
* function pointers set here are only for PHY-specific functions.
**/
s32 ixgbe_assign_func_pointers_phy(struct ixgbe_hw *hw)
{
hw->func.ixgbe_func_reset_phy =
&ixgbe_reset_phy_generic;
hw->func.ixgbe_func_read_phy_reg =
&ixgbe_read_phy_reg_generic;
hw->func.ixgbe_func_write_phy_reg =
&ixgbe_write_phy_reg_generic;
hw->func.ixgbe_func_identify_phy =
&ixgbe_identify_phy_generic;
if (ixgbe_get_media_type(hw) == ixgbe_media_type_copper) {
/* Call PHY identify routine to get the phy type */
ixgbe_identify_phy(hw);
switch (hw->phy.type) {
case ixgbe_phy_tn:
hw->func.ixgbe_func_setup_phy_link =
&ixgbe_setup_tnx_phy_link;
hw->func.ixgbe_func_check_phy_link =
&ixgbe_check_tnx_phy_link;
hw->func.ixgbe_func_setup_phy_link_speed =
&ixgbe_setup_tnx_phy_link_speed;
break;
default:
break;
}
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_identify_phy_generic - Get physical layer module
* @hw: pointer to hardware structure
*
* Determines the physical layer module found on the current adapter.
**/
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
{
s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
u32 phy_addr;
for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
if (ixgbe_validate_phy_addr(hw, phy_addr)) {
hw->phy.addr = phy_addr;
ixgbe_get_phy_id(hw);
hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
status = IXGBE_SUCCESS;
break;
}
}
return status;
}
/**
* ixgbe_validate_phy_addr - Determines phy address is valid
* @hw: pointer to hardware structure
*
**/
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
{
u16 phy_id = 0;
bool valid = FALSE;
hw->phy.addr = phy_addr;
ixgbe_read_phy_reg_generic(hw,
IXGBE_MDIO_PHY_ID_HIGH,
IXGBE_MDIO_PMA_PMD_DEV_TYPE,
&phy_id);
if (phy_id != 0xFFFF && phy_id != 0x0)
valid = TRUE;
return valid;
}
/**
* ixgbe_get_phy_id - Get the phy type
* @hw: pointer to hardware structure
*
**/
s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
{
u32 status;
u16 phy_id_high = 0;
u16 phy_id_low = 0;
status = ixgbe_read_phy_reg_generic(hw,
IXGBE_MDIO_PHY_ID_HIGH,
IXGBE_MDIO_PMA_PMD_DEV_TYPE,
&phy_id_high);
if (status == IXGBE_SUCCESS) {
hw->phy.id = (u32)(phy_id_high << 16);
status = ixgbe_read_phy_reg_generic(hw,
IXGBE_MDIO_PHY_ID_LOW,
IXGBE_MDIO_PMA_PMD_DEV_TYPE,
&phy_id_low);
hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
}
return status;
}
/**
* ixgbe_get_phy_type_from_id - Get the phy type
* @hw: pointer to hardware structure
*
**/
enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
{
enum ixgbe_phy_type phy_type;
switch (phy_id) {
case TN1010_PHY_ID:
phy_type = ixgbe_phy_tn;
break;
case QT2022_PHY_ID:
phy_type = ixgbe_phy_qt;
break;
default:
phy_type = ixgbe_phy_unknown;
break;
}
return phy_type;
}
/**
* ixgbe_reset_phy_generic - Performs a PHY reset
* @hw: pointer to hardware structure
**/
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
{
/*
* Perform soft PHY reset to the PHY_XS.
* This will cause a soft reset to the PHY
*/
return ixgbe_write_phy_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
IXGBE_MDIO_PHY_XS_DEV_TYPE,
IXGBE_MDIO_PHY_XS_RESET);
}
/**
* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
* @phy_data: Pointer to read data from PHY register
**/
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 *phy_data)
{
u32 command;
u32 i;
u32 timeout = 10;
u32 data;
s32 status = IXGBE_SUCCESS;
u16 gssr;
if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
gssr = IXGBE_GSSR_PHY1_SM;
else
gssr = IXGBE_GSSR_PHY0_SM;
if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
status = IXGBE_ERR_SWFW_SYNC;
if (status == IXGBE_SUCCESS) {
/* Setup and write the address cycle command */
command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
(IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
/*
* Check every 10 usec to see if the address cycle completed.
* The MDI Command bit will clear when the operation is
* complete
*/
for (i = 0; i < timeout; i++) {
usec_delay(10);
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
break;
}
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGFUNC("PHY address command did not complete.\n");
status = IXGBE_ERR_PHY;
}
if (status == IXGBE_SUCCESS) {
/*
* Address cycle complete, setup and write the read
* command
*/
command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
(IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
/*
* Check every 10 usec to see if the address cycle
* completed. The MDI Command bit will clear when the
* operation is complete
*/
for (i = 0; i < timeout; i++) {
usec_delay(10);
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGFUNC("PHY read command didn't complete\n");
status = IXGBE_ERR_PHY;
} else {
/*
* Read operation is complete. Get the data
* from MSRWD
*/
data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
*phy_data = (u16)(data);
}
}
ixgbe_release_swfw_sync(hw, gssr);
}
return status;
}
/**
* ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
* @device_type: 5 bit device type
* @phy_data: Data to write to the PHY register
**/
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 phy_data)
{
u32 command;
u32 i;
u32 timeout = 10;
s32 status = IXGBE_SUCCESS;
u16 gssr;
if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
gssr = IXGBE_GSSR_PHY1_SM;
else
gssr = IXGBE_GSSR_PHY0_SM;
if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
status = IXGBE_ERR_SWFW_SYNC;
if (status == IXGBE_SUCCESS) {
/* Put the data in the MDI single read and write data register*/
IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
/* Setup and write the address cycle command */
command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
(IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
/*
* Check every 10 usec to see if the address cycle completed.
* The MDI Command bit will clear when the operation is
* complete
*/
for (i = 0; i < timeout; i++) {
usec_delay(10);
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
DEBUGFUNC("PHY address cmd didn't complete\n");
break;
}
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0)
status = IXGBE_ERR_PHY;
if (status == IXGBE_SUCCESS) {
/*
* Address cycle complete, setup and write the write
* command
*/
command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
(IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
/*
* Check every 10 usec to see if the address cycle
* completed. The MDI Command bit will clear when the
* operation is complete
*/
for (i = 0; i < timeout; i++) {
usec_delay(10);
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
DEBUGFUNC("PHY write command did not "
"complete.\n");
break;
}
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0)
status = IXGBE_ERR_PHY;
}
ixgbe_release_swfw_sync(hw, gssr);
}
return status;
}
/**
* ixgbe_setup_phy_link - Restart PHY autoneg
* @hw: pointer to hardware structure
*
* Restart autonegotiation and PHY and waits for completion.
**/
s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, ixgbe_func_setup_phy_link, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_check_phy_link - Determine link and speed status
* @hw: pointer to hardware structure
*
* Reads a PHY register to determine if link is up and the current speed for
* the PHY.
**/
s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *link_up)
{
return ixgbe_call_func(hw, ixgbe_func_check_phy_link, (hw, speed,
link_up), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_setup_phy_link_speed - Set auto advertise
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: TRUE if autonegotiation enabled
*
* Sets the auto advertised capabilities
**/
s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
bool autoneg,
bool autoneg_wait_to_complete)
{
return ixgbe_call_func(hw, ixgbe_func_setup_phy_link_speed, (hw, speed,
autoneg, autoneg_wait_to_complete),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_setup_tnx_phy_link - Set and restart autoneg
* @hw: pointer to hardware structure
*
* Restart autonegotiation and PHY and waits for completion.
**/
s32 ixgbe_setup_tnx_phy_link(struct ixgbe_hw *hw)
{
s32 status = IXGBE_NOT_IMPLEMENTED;
u32 time_out;
u32 max_time_out = 10;
u16 autoneg_speed_selection_register = 0x10;
u16 autoneg_restart_mask = 0x0200;
u16 autoneg_complete_mask = 0x0020;
u16 autoneg_reg = 0;
/*
* Set advertisement settings in PHY based on autoneg_advertised
* settings. If autoneg_advertised = 0, then advertise default values
* txn devices cannot be "forced" to a autoneg 10G and fail. But can
* for a 1G.
*/
ixgbe_read_phy_reg(hw,
autoneg_speed_selection_register,
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
&autoneg_reg);
if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
else
autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
ixgbe_write_phy_reg(hw,
autoneg_speed_selection_register,
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
autoneg_reg);
/* Restart PHY autonegotiation and wait for completion */
ixgbe_read_phy_reg(hw,
IXGBE_MDIO_AUTO_NEG_CONTROL,
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
&autoneg_reg);
autoneg_reg |= autoneg_restart_mask;
ixgbe_write_phy_reg(hw,
IXGBE_MDIO_AUTO_NEG_CONTROL,
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
autoneg_reg);
/* Wait for autonegotiation to finish */
for (time_out = 0; time_out < max_time_out; time_out++) {
usec_delay(10);
/* Restart PHY autonegotiation and wait for completion */
status = ixgbe_read_phy_reg(hw,
IXGBE_MDIO_AUTO_NEG_STATUS,
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
&autoneg_reg);
autoneg_reg &= autoneg_complete_mask;
if (autoneg_reg == autoneg_complete_mask) {
status = IXGBE_SUCCESS;
break;
}
}
if (time_out == max_time_out)
status = IXGBE_ERR_LINK_SETUP;
return status;
}
/**
* ixgbe_check_tnx_phy_link - Determine link and speed status
* @hw: pointer to hardware structure
*
* Reads the VS1 register to determine if link is up and the current speed for
* the PHY.
**/
s32 ixgbe_check_tnx_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *link_up)
{
s32 status = IXGBE_SUCCESS;
u32 time_out;
u32 max_time_out = 10;
u16 phy_link = 0;
u16 phy_speed = 0;
u16 phy_data = 0;
/* Initialize speed and link to default case */
*link_up = FALSE;
*speed = IXGBE_LINK_SPEED_10GB_FULL;
/*
* Check current speed and link status of the PHY register.
* This is a vendor specific register and may have to
* be changed for other copper PHYs.
*/
for (time_out = 0; time_out < max_time_out; time_out++) {
usec_delay(10);
if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
*link_up = TRUE;
if (phy_speed ==
IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
*speed = IXGBE_LINK_SPEED_1GB_FULL;
break;
} else {
status = ixgbe_read_phy_reg(hw,
IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
&phy_data);
phy_link = phy_data &
IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
phy_speed = phy_data &
IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
}
}
return status;
}
/**
* ixgbe_setup_tnx_phy_link_speed - Sets the auto advertised capabilities
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: TRUE if autonegotiation enabled
**/
s32 ixgbe_setup_tnx_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
bool autoneg,
bool autoneg_wait_to_complete)
{
UNREFERENCED_PARAMETER(autoneg);
UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
/*
* Clear autoneg_advertised and set new values based on input link
* speed.
*/
hw->phy.autoneg_advertised = 0;
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
}
/* Setup link based on the new speed settings */
ixgbe_setup_tnx_phy_link(hw);
return IXGBE_SUCCESS;
}

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/*******************************************************************************
Copyright (c) 2001-2007, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* $FreeBSD$ */
#ifndef _IXGBE_PHY_H_
#define _IXGBE_PHY_H_
#include "ixgbe_type.h"
s32 ixgbe_init_shared_code_phy(struct ixgbe_hw *hw);
s32 ixgbe_assign_func_pointers_phy(struct ixgbe_hw *hw);
s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
bool *link_up);
s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
bool autoneg,
bool autoneg_wait_to_complete);
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 *phy_data);
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 phy_data);
/* PHY specific */
s32 ixgbe_setup_tnx_phy_link(struct ixgbe_hw *hw);
s32 ixgbe_check_tnx_phy_link(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
bool *link_up);
s32 ixgbe_setup_tnx_phy_link_speed(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
bool autoneg,
bool autoneg_wait_to_complete);
#endif /* _IXGBE_PHY_H_ */

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