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Put in offset definitions for FPM and FBM registers, plus just enough
bits defined so we can reset them.
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parent
df1590c05d
commit
144ff11903
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=71078
@ -349,6 +349,19 @@
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#define MAX_MAILBOX 8
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/*
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* Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00).
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* NB: The RISC processor must be paused and the appropriate register
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* bank selected via BIU2100_CSR bits.
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*/
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#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96)
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#define FPM_SOFT_RESET 0x0100
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#define FBM_CMD (BIU_BLOCK + 0xB8)
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#define FBMCMD_FIFO_RESET_ALL 0xA000
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/*
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* SXP Block Register Offsets
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*/
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@ -601,6 +614,10 @@
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#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */
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#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */
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#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */
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#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /*
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* Disable RISC pause on FPM
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* parity error.
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*/
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#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */
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#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */
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#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */
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