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Add support for 64bit addressing to AHCI and Marvell controllers.
Munged into ATA shape and Marvell specifics my yours truely. Submitted by: jhb
This commit is contained in:
Søren Schmidt
parent
9dd50a972f
commit
16194fc40b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=168430
@ -445,6 +445,7 @@ struct ata_dma {
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#define ATA_DMA_READ 0x01 /* transaction is a read */
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#define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */
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#define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */
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#define ATA_DMA_64BIT 0x10 /* supports 64bit addressing */
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void (*alloc)(device_t dev);
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void (*free)(device_t dev);
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@ -503,6 +503,7 @@ ata_ahci_allocate(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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u_int64_t work;
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int offset = ch->unit << 7;
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/* set the SATA resources */
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@ -521,13 +522,13 @@ ata_ahci_allocate(device_t dev)
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ch->hw.command = NULL; /* not used here */
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/* setup work areas */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset,
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ch->dma->work_bus + ATA_AHCI_CL_OFFSET);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, 0x00000000);
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work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset,
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ch->dma->work_bus + ATA_AHCI_FB_OFFSET);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, 0x00000000);
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work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
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/* enable wanted port interrupts */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
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@ -766,6 +767,7 @@ ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
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static void
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ata_ahci_dmainit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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ata_dmainit(dev);
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@ -773,6 +775,8 @@ ata_ahci_dmainit(device_t dev)
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/* note start and stop are not used here */
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ch->dma->setprd = ata_ahci_dmasetprd;
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ch->dma->max_iosize = 8192 * DEV_BSIZE;
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if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
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ch->dma->flags |= ATA_DMA_64BIT;
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}
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}
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@ -2417,7 +2421,7 @@ ata_marvell_edma_allocate(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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bus_addr_t work = ch->dma->work_bus;
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u_int64_t work = ch->dma->work_bus;
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int i;
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/* clear work area */
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@ -2470,7 +2474,7 @@ ata_marvell_edma_allocate(device_t dev)
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ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
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/* request queue base high */
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ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), (work >> 16) >> 16);
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ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
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/* request queue in ptr */
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ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
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@ -2480,7 +2484,7 @@ ata_marvell_edma_allocate(device_t dev)
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/* response queue base high */
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work += 1024;
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ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), (work >> 16) >> 16);
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ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
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/* response queue in ptr */
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ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
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@ -2568,7 +2572,7 @@ ata_marvell_edma_begin_transaction(struct ata_request *request)
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/* fill in this request */
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quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
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quadp[1] = (ch->dma->sg_bus & 0xffffffff00000000ull) >> 32;
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quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
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wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
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i = 10;
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@ -2721,12 +2725,17 @@ ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
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static void
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ata_marvell_edma_dmainit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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ata_dmainit(dev);
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if (ch->dma) {
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/* note start and stop are not used here */
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ch->dma->setprd = ata_marvell_edma_dmasetprd;
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device_printf(dev, "HW qword=%08x\n", ATA_INL(ctlr->r_res1, 0x00d00));
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if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
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ch->dma->flags |= ATA_DMA_64BIT;
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}
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}
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@ -95,22 +95,24 @@ ata_dmaalloc(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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struct ata_dc_cb_args ccba;
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int maxaddr = (ch->dma->flags & ATA_DMA_64BIT ?
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BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT);
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if (bus_dma_tag_create(bus_get_dma_tag(dev), ch->dma->alignment, 0,
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BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
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maxaddr, BUS_SPACE_MAXADDR,
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NULL, NULL, ch->dma->max_iosize,
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ATA_DMA_ENTRIES, ch->dma->segsize,
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0, NULL, NULL, &ch->dma->dmatag))
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goto error;
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if (bus_dma_tag_create(ch->dma->dmatag, PAGE_SIZE, PAGE_SIZE,
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BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
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maxaddr, BUS_SPACE_MAXADDR,
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NULL, NULL, MAXTABSZ, 1, MAXTABSZ,
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0, NULL, NULL, &ch->dma->sg_tag))
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goto error;
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if (bus_dma_tag_create(ch->dma->dmatag,ch->dma->alignment,ch->dma->boundary,
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BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
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maxaddr, BUS_SPACE_MAXADDR,
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NULL, NULL, ch->dma->max_iosize,
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ATA_DMA_ENTRIES, ch->dma->segsize,
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0, NULL, NULL, &ch->dma->data_tag))
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@ -131,7 +133,7 @@ ata_dmaalloc(device_t dev)
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goto error;
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if (bus_dma_tag_create(ch->dma->dmatag, PAGE_SIZE, 64 * 1024,
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BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
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maxaddr, BUS_SPACE_MAXADDR,
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NULL, NULL, MAXWSPCSZ, 1, MAXWSPCSZ,
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0, NULL, NULL, &ch->dma->work_tag))
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goto error;
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@ -102,6 +102,7 @@ ata_begin_transaction(struct ata_request *request)
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/* device reset doesn't interrupt */
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if (request->u.ata.command == ATA_DEVICE_RESET) {
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int timeout = 1000000;
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do {
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DELAY(10);
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@ -1,4 +1,4 @@
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# Copyright (c) 2004 - 2006 Søren Schmidt <sos@FreeBSD.org>
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# Copyright (c) 2004 - 2007 Søren Schmidt <sos@FreeBSD.org>
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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