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- Add an entry for the SIIG Cyber 2SP1 PCIe adapter, which is based
on an Oxford Semiconductor OX16PCI954 but uses only two ports and a non-default clock rate. - Fix style/whitespace PR: 176407 MFC after: 3 days
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parent
7aedea5357
commit
1714dcab20
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=292840
@ -763,6 +763,12 @@ const struct puc_cfg puc_pci_devices[] = {
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PUC_PORT_4S, 0x10, 0, 8,
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},
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{ 0x1415, 0x950a, 0x131f, 0x2061,
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"SIIG Cyber 2SP1 PCIe",
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DEFAULT_RCLK * 10,
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PUC_PORT_2S, 0x10, 0, 8,
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},
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{ 0x1415, 0x950a, 0xffff, 0,
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"Oxford Semiconductor OX16PCI954 UARTs",
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DEFAULT_RCLK,
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@ -840,9 +846,9 @@ const struct puc_cfg puc_pci_devices[] = {
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*/
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{ 0x1415, 0xc11b, 0xffff, 0,
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"Oxford Semiconductor OXPCIe952 1S1P",
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DEFAULT_RCLK * 0x22,
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PUC_PORT_NONSTANDARD, 0x10, 0, -1,
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"Oxford Semiconductor OXPCIe952 1S1P",
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DEFAULT_RCLK * 0x22,
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PUC_PORT_NONSTANDARD, 0x10, 0, -1,
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.config_function = puc_config_oxford_pcie
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},
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@ -1275,7 +1281,8 @@ puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
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if (cmd == PUC_CFG_GET_OFS) {
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const struct puc_cfg *cfg = sc->sc_cfg;
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if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144))
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if (port == 3 && (cfg->device == 0x1045 ||
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cfg->device == 0x1144))
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port = 7;
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*res = port * 0x200;
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