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The POWER7 has only 32 SLB slots instead of 64, like other supported
64-bit PowerPC CPUs. Add infrastructure to support variable numbers of SLB slots and move the user slot from 63 to 0, so that it is always available.
This commit is contained in:
Nathan Whitehorn
parent
d63d020e22
commit
17763042e4
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=222620
@ -132,6 +132,7 @@ extern vm_offset_t ksym_start, ksym_end;
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int cold = 1;
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#ifdef __powerpc64__
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extern int n_slbs;
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int cacheline_size = 128;
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#else
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int cacheline_size = 32;
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@ -337,13 +338,13 @@ powerpc_init(vm_offset_t startkernel, vm_offset_t endkernel,
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kdb_init();
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/*
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* PowerPC 970 CPUs have a misfeature requested by Apple that makes
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* them pretend they have a 32-byte cacheline. Turn this off
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* before we measure the cacheline size.
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*/
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/* Various very early CPU fix ups */
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switch (mfpvr() >> 16) {
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/*
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* PowerPC 970 CPUs have a misfeature requested by Apple that
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* makes them pretend they have a 32-byte cacheline. Turn this
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* off before we measure the cacheline size.
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*/
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case IBM970:
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case IBM970FX:
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case IBM970MP:
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@ -352,6 +353,12 @@ powerpc_init(vm_offset_t startkernel, vm_offset_t endkernel,
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scratch &= ~HID5_970_DCBZ_SIZE_HI;
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mtspr(SPR_HID5, scratch);
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break;
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#ifdef __powerpc64__
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case IBMPOWER7:
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/* XXX: get from ibm,slb-size in device tree */
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n_slbs = 32;
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break;
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#endif
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}
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/*
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@ -367,7 +374,6 @@ powerpc_init(vm_offset_t startkernel, vm_offset_t endkernel,
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msr = mfmsr();
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mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI);
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isync();
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/*
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* Measure the cacheline size using dcbz
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@ -502,7 +508,6 @@ powerpc_init(vm_offset_t startkernel, vm_offset_t endkernel,
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* Restore MSR
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*/
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mtmsr(msr);
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isync();
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/* Warn if cachline size was not determined */
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if (cacheline_warn == 1) {
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@ -527,7 +532,6 @@ powerpc_init(vm_offset_t startkernel, vm_offset_t endkernel,
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pmap_bootstrap(startkernel, endkernel);
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mtmsr(PSL_KERNSET & ~PSL_EE);
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isync();
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/*
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* Initialize params/tunables that are derived from memsize
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@ -51,8 +51,9 @@ uintptr_t moea64_get_unique_vsid(void);
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void moea64_release_vsid(uint64_t vsid);
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static void slb_zone_init(void *);
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uma_zone_t slbt_zone;
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uma_zone_t slb_cache_zone;
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static uma_zone_t slbt_zone;
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static uma_zone_t slb_cache_zone;
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int n_slbs = 64;
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SYSINIT(slb_zone_init, SI_SUB_KMEM, SI_ORDER_ANY, slb_zone_init, NULL);
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@ -426,16 +427,18 @@ slb_insert_kernel(uint64_t slbe, uint64_t slbv)
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/* Check for an unused slot, abusing the user slot as a full flag */
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if (slbcache[USER_SLB_SLOT].slbe == 0) {
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for (i = 0; i < USER_SLB_SLOT; i++) {
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for (i = 0; i < n_slbs; i++) {
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if (i == USER_SLB_SLOT)
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continue;
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if (!(slbcache[i].slbe & SLBE_VALID))
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goto fillkernslb;
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}
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if (i == USER_SLB_SLOT)
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if (i == n_slbs)
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slbcache[USER_SLB_SLOT].slbe = 1;
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}
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for (i = mftb() % 64, j = 0; j < 64; j++, i = (i+1) % 64) {
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for (i = mftb() % n_slbs, j = 0; j < n_slbs; j++, i = (i+1) % n_slbs) {
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if (i == USER_SLB_SLOT)
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continue;
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@ -443,9 +446,11 @@ slb_insert_kernel(uint64_t slbe, uint64_t slbv)
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break;
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}
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KASSERT(j < 64, ("All kernel SLB slots locked!"));
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KASSERT(j < n_slbs, ("All kernel SLB slots locked!"));
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fillkernslb:
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KASSERT(i != USER_SLB_SLOT,
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("Filling user SLB slot with a kernel mapping"));
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slbcache[i].slbv = slbv;
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slbcache[i].slbe = slbe | (uint64_t)i;
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@ -466,11 +471,11 @@ slb_insert_user(pmap_t pm, struct slb *slb)
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PMAP_LOCK_ASSERT(pm, MA_OWNED);
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if (pm->pm_slb_len < 64) {
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if (pm->pm_slb_len < n_slbs) {
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i = pm->pm_slb_len;
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pm->pm_slb_len++;
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} else {
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i = mftb() % 64;
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i = mftb() % n_slbs;
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}
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/* Note that this replacement is atomic with respect to trap_subr */
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@ -521,8 +526,9 @@ slb_zone_init(void *dummy)
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slbt_zone = uma_zcreate("SLB tree node", sizeof(struct slbtnode),
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NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM);
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slb_cache_zone = uma_zcreate("SLB cache", 64*sizeof(struct slb *),
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NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM);
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slb_cache_zone = uma_zcreate("SLB cache",
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(n_slbs + 1)*sizeof(struct slb *), NULL, NULL, NULL, NULL,
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UMA_ALIGN_PTR, UMA_ZONE_VM);
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if (platform_real_maxaddr() != VM_MAX_ADDRESS) {
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uma_zone_set_allocf(slb_cache_zone, slb_uma_real_alloc);
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@ -53,55 +53,53 @@
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* User SRs are loaded through a pointer to the current pmap.
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*/
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restore_usersrs:
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GET_CPUINFO(%r28);
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ld %r28,PC_USERSLB(%r28);
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GET_CPUINFO(%r28)
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ld %r28,PC_USERSLB(%r28)
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li %r29, 0 /* Set the counter to zero */
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slbia
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slbmfee %r31,%r29
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clrrdi %r31,%r31,28
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slbie %r31
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instuserslb:
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ld %r31, 0(%r28); /* Load SLB entry pointer */
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cmpli 0, %r31, 0; /* If NULL, stop */
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beqlr;
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1: ld %r31, 0(%r28) /* Load SLB entry pointer */
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cmpli 0, %r31, 0 /* If NULL, stop */
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beqlr
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ld %r30, 0(%r31) /* Load SLBV */
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ld %r31, 8(%r31) /* Load SLBE */
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or %r31, %r31, %r29 /* Set SLBE slot */
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slbmte %r30, %r31; /* Install SLB entry */
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slbmte %r30, %r31 /* Install SLB entry */
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addi %r28, %r28, 8; /* Advance pointer */
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addi %r29, %r29, 1;
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cmpli 0, %r29, 64; /* Repeat if we are not at the end */
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blt instuserslb;
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blr;
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addi %r28, %r28, 8 /* Advance pointer */
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addi %r29, %r29, 1
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b 1b /* Repeat */
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/*
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* Kernel SRs are loaded directly from the PCPU fields
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*/
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restore_kernsrs:
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GET_CPUINFO(%r28);
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addi %r28,%r28,PC_KERNSLB;
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GET_CPUINFO(%r28)
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addi %r28,%r28,PC_KERNSLB
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li %r29, 0 /* Set the counter to zero */
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slbia
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slbmfee %r31,%r29
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clrrdi %r31,%r31,28
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slbie %r31
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instkernslb:
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ld %r31, 8(%r28); /* Load SLBE */
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1: cmpli 0, %r29, USER_SLB_SLOT /* Skip the user slot */
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beq- 2f
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cmpli 0, %r31, 0; /* If SLBE is not valid, stop */
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beqlr;
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ld %r31, 8(%r28) /* Load SLBE */
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cmpli 0, %r31, 0 /* If SLBE is not valid, stop */
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beqlr
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ld %r30, 0(%r28) /* Load SLBV */
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slbmte %r30, %r31; /* Install SLB entry */
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slbmte %r30, %r31 /* Install SLB entry */
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addi %r28, %r28, 16; /* Advance pointer */
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addi %r29, %r29, 1;
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cmpli 0, %r29, USER_SLB_SLOT; /* Repeat if we are not at the end */
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blt instkernslb;
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blr;
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2: addi %r28, %r28, 16 /* Advance pointer */
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addi %r29, %r29, 1
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cmpli 0, %r29, 64 /* Repeat if we are not at the end */
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blt 1b
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blr
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/*
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* FRAME_SETUP assumes:
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@ -65,7 +65,7 @@
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/*
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* User segment for copyin/out
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*/
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#define USER_SLB_SLOT 63
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#define USER_SLB_SLOT 0
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#define USER_SLB_SLBE (((USER_ADDR >> ADDR_SR_SHFT) << SLBE_ESID_SHIFT) | \
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SLBE_VALID | USER_SLB_SLOT)
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