1
0
mirror of https://git.FreeBSD.org/src.git synced 2025-01-01 12:19:28 +00:00

Add some PHY magic to enable PHY hibernation and 1000baseT/10baseT

power adjustment. This change is required to guarantee correct
operation on certain switches.

Submitted by:	Jie Yang < Jie.Yang <> Atheros com >
This commit is contained in:
Pyun YongHyeon 2008-12-03 08:56:01 +00:00
parent 1f9cbabcdb
commit 19042fb8c7
Notes: svn2git 2020-12-20 02:59:44 +00:00
svn path=/head/; revision=185576

View File

@ -385,6 +385,39 @@ ale_phy_reset(struct ale_softc *sc)
GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
DELAY(1000);
#define ATPHY_DBG_ADDR 0x1D
#define ATPHY_DBG_DATA 0x1E
/* Enable hibernation mode. */
ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
ATPHY_DBG_ADDR, 0x0B);
ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
ATPHY_DBG_DATA, 0xBC00);
/* Set Class A/B for all modes. */
ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
ATPHY_DBG_ADDR, 0x00);
ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
ATPHY_DBG_DATA, 0x02EF);
/* Enable 10BT power saving. */
ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
ATPHY_DBG_ADDR, 0x12);
ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
ATPHY_DBG_DATA, 0x4C04);
/* Adjust 1000T power. */
ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
ATPHY_DBG_ADDR, 0x04);
ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
ATPHY_DBG_ADDR, 0x8BBB);
/* 10BT center tap voltage. */
ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
ATPHY_DBG_ADDR, 0x05);
ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
ATPHY_DBG_ADDR, 0x2C46);
#undef ATPHY_DBG_ADDR
#undef ATPHY_DBG_DATA
DELAY(1000);
}
static int