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Add some PHY magic to enable PHY hibernation and 1000baseT/10baseT
power adjustment. This change is required to guarantee correct operation on certain switches. Submitted by: Jie Yang < Jie.Yang <> Atheros com >
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19042fb8c7
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=185576
@ -385,6 +385,39 @@ ale_phy_reset(struct ale_softc *sc)
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GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
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GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
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DELAY(1000);
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#define ATPHY_DBG_ADDR 0x1D
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#define ATPHY_DBG_DATA 0x1E
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/* Enable hibernation mode. */
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ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
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ATPHY_DBG_ADDR, 0x0B);
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ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
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ATPHY_DBG_DATA, 0xBC00);
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/* Set Class A/B for all modes. */
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ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
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ATPHY_DBG_ADDR, 0x00);
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ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
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ATPHY_DBG_DATA, 0x02EF);
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/* Enable 10BT power saving. */
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ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
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ATPHY_DBG_ADDR, 0x12);
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ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
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ATPHY_DBG_DATA, 0x4C04);
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/* Adjust 1000T power. */
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ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
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ATPHY_DBG_ADDR, 0x04);
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ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
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ATPHY_DBG_ADDR, 0x8BBB);
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/* 10BT center tap voltage. */
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ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
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ATPHY_DBG_ADDR, 0x05);
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ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
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ATPHY_DBG_ADDR, 0x2C46);
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#undef ATPHY_DBG_ADDR
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#undef ATPHY_DBG_DATA
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DELAY(1000);
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}
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static int
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