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Convert to use bus_dmamap_load_mbuf(); decouple software TX descriptors
from the hardware descriptors to avoid the overhead of having a DMA map for each of them. Bump the number of hardware descriptors to 128, and use half as many software descriptors for now. Some minor cleanups.
This commit is contained in:
Thomas Moestl
parent
a5c6189066
commit
195530b9dd
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=108834
@ -1,6 +1,6 @@
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org>.
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* Copyright (c) 2001-2003 Thomas Moestl <tmm@FreeBSD.org>.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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@ -105,15 +105,17 @@ static void hme_setladrf(struct hme_softc *, int);
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static int hme_mediachange(struct ifnet *);
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static void hme_mediastatus(struct ifnet *, struct ifmediareq *);
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static int hme_load_mbuf(struct hme_softc *, struct mbuf *);
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static int hme_load_txmbuf(struct hme_softc *, struct mbuf *);
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static void hme_read(struct hme_softc *, int, int);
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static void hme_eint(struct hme_softc *, u_int);
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static void hme_rint(struct hme_softc *);
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static void hme_tint(struct hme_softc *);
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static void hme_cdma_callback(void *, bus_dma_segment_t *, int, int);
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static void hme_rxdma_callback(void *, bus_dma_segment_t *, int, int);
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static void hme_txdma_callback(void *, bus_dma_segment_t *, int, int);
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static void hme_rxdma_callback(void *, bus_dma_segment_t *, int,
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bus_size_t, int);
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static void hme_txdma_callback(void *, bus_dma_segment_t *, int,
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bus_size_t, int);
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devclass_t hme_devclass;
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@ -252,9 +254,8 @@ hme_config(struct hme_softc *sc)
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if (error != 0)
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goto fail_rxdesc;
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/* Same for the TX descs. */
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for (tdesc = 0; tdesc < HME_NTXDESC; tdesc++) {
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for (tdesc = 0; tdesc < HME_NTXQ; tdesc++) {
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sc->sc_rb.rb_txdesc[tdesc].htx_m = NULL;
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sc->sc_rb.rb_txdesc[tdesc].htx_flags = 0;
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error = bus_dmamap_create(sc->sc_tdmatag, 0,
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&sc->sc_rb.rb_txdesc[tdesc].htx_dmamap);
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if (error != 0)
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@ -277,7 +278,7 @@ hme_config(struct hme_softc *sc)
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ifp->if_init = hme_init;
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ifp->if_output = ether_output;
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ifp->if_watchdog = hme_watchdog;
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ifp->if_snd.ifq_maxlen = HME_NTXDESC;
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ifp->if_snd.ifq_maxlen = HME_NTXQ;
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hme_mifinit(sc);
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@ -401,12 +402,13 @@ hme_stop(struct hme_softc *sc)
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}
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static void
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hme_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
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hme_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs,
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bus_size_t totsize, int error)
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{
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bus_addr_t *a = xsc;
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/* XXX: A cluster should not contain more than one segment, correct? */
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if (error != 0 || nsegs != 1)
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KASSERT(nsegs == 1, ("hme_rxdma_callback: multiple segments!"));
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if (error != 0)
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return;
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*a = segs[0].ds_addr;
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}
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@ -424,8 +426,7 @@ hme_discard_rxbuf(struct hme_softc *sc, int ix, int sync)
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* ownership back to the hardware.
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*/
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HME_XD_SETFLAGS(sc->sc_pci, sc->sc_rb.rb_rxd, ix, HME_XD_OWN |
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HME_XD_ENCODE_RSIZE(ulmin(HME_BUFSZ,
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sc->sc_rb.rb_rxdesc[ix].hrx_len)));
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HME_XD_ENCODE_RSIZE(HME_DESC_RXLEN(sc, &sc->sc_rb.rb_rxdesc[ix])));
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if (sync) {
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bus_dmamap_sync(sc->sc_cdmatag, sc->sc_cdmamap,
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BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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@ -438,10 +439,9 @@ hme_add_rxbuf(struct hme_softc *sc, unsigned int ri, int keepold)
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struct hme_rxdesc *rd;
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struct mbuf *m;
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bus_addr_t ba;
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bus_size_t len, offs;
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bus_dmamap_t map;
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uintptr_t b;
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int a, unmap;
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char *b;
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rd = &sc->sc_rb.rb_rxdesc[ri];
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unmap = rd->hrx_m != NULL;
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@ -453,33 +453,29 @@ hme_add_rxbuf(struct hme_softc *sc, unsigned int ri, int keepold)
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hme_discard_rxbuf(sc, ri, 0);
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return (0);
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}
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if ((m = m_gethdr(M_DONTWAIT, MT_DATA)) == NULL)
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if ((m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR)) == NULL)
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return (ENOBUFS);
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m_clget(m, M_DONTWAIT);
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if ((m->m_flags & M_EXT) == 0)
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goto fail_mcl;
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len = m->m_ext.ext_size;
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b = mtod(m, char *);
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m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
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b = mtod(m, uintptr_t);
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/*
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* Required alignment boundary. At least 16 is needed, but since
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* the mapping must be done in a way that a burst can start on a
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* natural boundary we might need to extend this.
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*/
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a = max(0x10, sc->sc_burst);
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a = max(HME_MINRXALIGN, sc->sc_burst);
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/*
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* Make sure the buffer suitably aligned: we need an offset of
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* 2 modulo a. XXX: this ensures at least 16 byte alignment of the
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* header adjacent to the ethernet header, which should be sufficient
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* in all cases. Nevertheless, this second-guesses ALIGN().
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* Make sure the buffer suitably aligned. The 2 byte offset is removed
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* when the mbuf is handed up. XXX: this ensures at least 16 byte
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* alignment of the header adjacent to the ethernet header, which
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* should be sufficient in all cases. Nevertheless, this second-guesses
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* ALIGN().
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*/
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offs = (a - (((uintptr_t)b - 2) & (a - 1))) % a;
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len -= offs;
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/* Align the buffer on the boundary for mapping. */
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b += offs - 2;
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ba = 0;
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if (bus_dmamap_load(sc->sc_rdmatag, sc->sc_rb.rb_spare_dmamap,
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b, len + 2, hme_rxdma_callback, &ba, 0) != 0 || ba == 0)
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goto fail_mcl;
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m_adj(m, roundup2(b, a) - b);
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if (bus_dmamap_load_mbuf(sc->sc_rdmatag, sc->sc_rb.rb_spare_dmamap,
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m, hme_rxdma_callback, &ba, 0) != 0) {
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m_freem(m);
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return (ENOBUFS);
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}
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if (unmap) {
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bus_dmamap_sync(sc->sc_rdmatag, rd->hrx_dmamap,
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BUS_DMASYNC_POSTREAD);
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@ -488,19 +484,12 @@ hme_add_rxbuf(struct hme_softc *sc, unsigned int ri, int keepold)
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map = rd->hrx_dmamap;
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rd->hrx_dmamap = sc->sc_rb.rb_spare_dmamap;
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sc->sc_rb.rb_spare_dmamap = map;
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rd->hrx_offs = offs;
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rd->hrx_len = len - sc->sc_burst;
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bus_dmamap_sync(sc->sc_rdmatag, rd->hrx_dmamap, BUS_DMASYNC_PREREAD);
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HME_XD_SETADDR(sc->sc_pci, sc->sc_rb.rb_rxd, ri, ba);
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/* Lazily leave at least one burst size grace space. */
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HME_XD_SETFLAGS(sc->sc_pci, sc->sc_rb.rb_rxd, ri, HME_XD_OWN |
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HME_XD_ENCODE_RSIZE(ulmin(HME_BUFSZ, rd->hrx_len)));
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rd->hrx_m = m;
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HME_XD_SETFLAGS(sc->sc_pci, sc->sc_rb.rb_rxd, ri, HME_XD_OWN |
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HME_XD_ENCODE_RSIZE(HME_DESC_RXLEN(sc, rd)));
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return (0);
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fail_mcl:
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m_freem(m);
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return (ENOBUFS);
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}
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static int
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@ -542,16 +531,20 @@ hme_meminit(struct hme_softc *sc)
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* Initialize transmit buffer descriptors
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*/
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for (i = 0; i < HME_NTXDESC; i++) {
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td = &sc->sc_rb.rb_txdesc[i];
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HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, 0);
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HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0);
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}
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STAILQ_INIT(&sc->sc_rb.rb_txfreeq);
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STAILQ_INIT(&sc->sc_rb.rb_txbusyq);
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for (i = 0; i < HME_NTXQ; i++) {
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td = &sc->sc_rb.rb_txdesc[i];
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if (td->htx_m != NULL) {
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m_freem(td->htx_m);
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bus_dmamap_unload(sc->sc_tdmatag, td->htx_dmamap);
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td->htx_m = NULL;
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}
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if ((td->htx_flags & HTXF_MAPPED) != 0)
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bus_dmamap_unload(sc->sc_tdmatag, td->htx_dmamap);
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td->htx_flags = 0;
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STAILQ_INSERT_TAIL(&sc->sc_rb.rb_txfreeq, td, htx_q);
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}
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/*
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@ -630,10 +623,6 @@ hme_init(void *xsc)
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/* Re-initialize the MIF */
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hme_mifinit(sc);
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/* Call MI reset function if any */
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if (sc->sc_hwreset)
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(*sc->sc_hwreset)(sc);
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#if 0
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/* Mask all MIF interrupts, just in case */
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HME_MIF_WRITE_4(sc, HME_MIFI_IMASK, 0xffff);
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@ -735,9 +724,9 @@ hme_init(void *xsc)
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break;
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}
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/* Enable DMA, fix RX first byte offset to 2. */
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/* Enable DMA, fix RX first byte offset. */
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v &= ~HME_ERX_CFG_FBO_MASK;
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v |= HME_ERX_CFG_DMAENABLE | (2 << HME_ERX_CFG_FBO_SHIFT);
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v |= HME_ERX_CFG_DMAENABLE | (HME_RXOFFS << HME_ERX_CFG_FBO_SHIFT);
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CTR1(KTR_HME, "hme_init: programming ERX_CFG to %x", (u_int)v);
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HME_ERX_WRITE_4(sc, HME_ERXI_CFG, v);
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@ -765,10 +754,6 @@ hme_init(void *xsc)
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/* step 14. Issue Transmit Pending command */
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/* Call MI initialization function if any */
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if (sc->sc_hwinit)
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(*sc->sc_hwinit)(sc);
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#ifdef HMEDEBUG
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/* Debug: double-check. */
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CTR4(KTR_HME, "hme_init: tx ring %#x, rsz %#x, rx ring %#x, "
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@ -795,85 +780,66 @@ hme_init(void *xsc)
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}
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struct hme_txdma_arg {
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struct hme_softc *hta_sc;
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struct mbuf *hta_m;
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int hta_err;
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int hta_flags;
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int hta_offs;
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int hta_pad;
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struct hme_softc *hta_sc;
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struct hme_txdesc *hta_htx;
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int hta_ndescs;
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};
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/* Values for hta_flags */
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#define HTAF_SOP 1 /* Start of packet (first mbuf in chain) */
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#define HTAF_EOP 2 /* Start of packet (last mbuf in chain) */
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/*
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* XXX: this relies on the fact that segments returned by bus_dmamap_load_mbuf()
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* are readable from the nearest burst boundary on (i.e. potentially before
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* ds_addr) to the first boundary beyond the end. This is usually a safe
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* assumption to make, but is not documented.
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*/
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static void
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hme_txdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
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hme_txdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs,
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bus_size_t totsz, int error)
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{
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struct hme_txdma_arg *ta = xsc;
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struct hme_txdesc *td;
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bus_addr_t addr;
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bus_size_t sz;
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struct hme_txdesc *htx;
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bus_size_t len = 0;
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caddr_t txd;
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u_int32_t flags;
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int i, *tdhead, pci;
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u_int32_t flags = 0;
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int i, tdhead, pci;
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ta->hta_err = error;
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if (error != 0)
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return;
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tdhead = &ta->hta_sc->sc_rb.rb_tdhead;
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tdhead = ta->hta_sc->sc_rb.rb_tdhead;
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pci = ta->hta_sc->sc_pci;
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txd = ta->hta_sc->sc_rb.rb_txd;
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htx = ta->hta_htx;
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if (ta->hta_sc->sc_rb.rb_td_nbusy + nsegs >= HME_NTXDESC) {
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ta->hta_ndescs = -1;
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return;
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}
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ta->hta_ndescs = nsegs;
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for (i = 0; i < nsegs; i++) {
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if (ta->hta_sc->sc_rb.rb_td_nbusy == HME_NTXDESC) {
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ta->hta_err = -1;
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return;
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}
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td = &ta->hta_sc->sc_rb.rb_txdesc[*tdhead];
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addr = segs[i].ds_addr;
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sz = segs[i].ds_len;
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if (i == 0) {
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/* Adjust the offsets. */
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addr += ta->hta_offs;
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sz -= ta->hta_offs;
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td->htx_flags = HTXF_MAPPED;
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} else
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td->htx_flags = 0;
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if (i == nsegs - 1) {
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/* Subtract the pad. */
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if (sz < ta->hta_pad) {
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/*
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* Ooops. This should not have happened; it
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* means that we got a zero-size segment or
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* segment sizes were unnatural.
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*/
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device_printf(ta->hta_sc->sc_dev,
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"hme_txdma_callback: alignment glitch\n");
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ta->hta_err = EINVAL;
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return;
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}
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sz -= ta->hta_pad;
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/* If sz is 0 now, this does not matter. */
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}
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if (segs[i].ds_len == 0)
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continue;
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/* Fill the ring entry. */
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flags = HME_XD_ENCODE_TSIZE(sz);
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if ((ta->hta_flags & HTAF_SOP) != 0 && i == 0)
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flags = HME_XD_ENCODE_TSIZE(segs[i].ds_len);
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if (len == 0)
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flags |= HME_XD_SOP;
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if ((ta->hta_flags & HTAF_EOP) != 0 && i == nsegs - 1) {
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if (len + segs[i].ds_len == totsz)
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flags |= HME_XD_EOP;
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td->htx_m = ta->hta_m;
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} else
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td->htx_m = NULL;
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CTR5(KTR_HME, "hme_txdma_callback: seg %d/%d, ri %d, "
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"flags %#x, addr %#x", i + 1, nsegs, *tdhead, (u_int)flags,
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(u_int)addr);
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HME_XD_SETFLAGS(pci, txd, *tdhead, flags);
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HME_XD_SETADDR(pci, txd, *tdhead, addr);
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"flags %#x, addr %#x", i + 1, nsegs, tdhead, (u_int)flags,
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(u_int)segs[i].ds_addr);
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HME_XD_SETFLAGS(pci, txd, tdhead, flags);
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HME_XD_SETADDR(pci, txd, tdhead, segs[i].ds_addr);
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ta->hta_sc->sc_rb.rb_td_nbusy++;
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*tdhead = ((*tdhead) + 1) % HME_NTXDESC;
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htx->htx_lastdesc = tdhead;
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tdhead = (tdhead + 1) % HME_NTXDESC;
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len += segs[i].ds_len;
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}
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ta->hta_sc->sc_rb.rb_tdhead = tdhead;
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KASSERT((flags & HME_XD_EOP) != 0,
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("hme_txdma_callback: missed end of packet!"));
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}
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/*
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@ -883,67 +849,32 @@ hme_txdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
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* the packet, or an errno otherwise.
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*/
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static int
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hme_load_mbuf(struct hme_softc *sc, struct mbuf *m0)
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hme_load_txmbuf(struct hme_softc *sc, struct mbuf *m0)
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{
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struct hme_txdma_arg cba;
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struct mbuf *m = m0, *n;
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struct hme_txdesc *td;
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char *start;
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int error, len, si, ri, totlen, sum;
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int error, si, ri;
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u_int32_t flags;
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if ((m->m_flags & M_PKTHDR) == 0)
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panic("hme_dmamap_load_mbuf: no packet header");
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totlen = m->m_pkthdr.len;
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sum = 0;
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si = sc->sc_rb.rb_tdhead;
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if ((td = STAILQ_FIRST(&sc->sc_rb.rb_txfreeq)) == NULL)
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return (-1);
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td->htx_m = m0;
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cba.hta_sc = sc;
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cba.hta_err = 0;
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cba.hta_flags = HTAF_SOP;
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cba.hta_m = m0;
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for (; m != NULL && sum < totlen; m = n) {
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if (sc->sc_rb.rb_td_nbusy == HME_NTXDESC) {
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error = -1;
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goto fail;
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}
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len = m->m_len;
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n = m->m_next;
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if (len == 0)
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continue;
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sum += len;
|
||||
td = &sc->sc_rb.rb_txdesc[sc->sc_rb.rb_tdhead];
|
||||
if (n == NULL || sum >= totlen)
|
||||
cba.hta_flags |= HTAF_EOP;
|
||||
/*
|
||||
* This is slightly evil: we must map the buffer in a way that
|
||||
* allows dma transfers to start on a natural burst boundary.
|
||||
* This is done by rounding down the mapping address, and
|
||||
* recording the required offset for the callback. With this,
|
||||
* we cannot cross a page boundary because the burst size
|
||||
* is a small power of two.
|
||||
*/
|
||||
cba.hta_offs = (sc->sc_burst -
|
||||
(mtod(m, uintptr_t) & (sc->sc_burst - 1))) % sc->sc_burst;
|
||||
start = mtod(m, char *) - cba.hta_offs;
|
||||
len += cba.hta_offs;
|
||||
/*
|
||||
* Similarly, the end of the mapping should be on a natural
|
||||
* burst boundary. XXX: Let's hope that any segment ends
|
||||
* generated by the busdma code are also on such boundaries.
|
||||
*/
|
||||
cba.hta_pad = (sc->sc_burst - (((uintptr_t)start + len) &
|
||||
(sc->sc_burst - 1))) % sc->sc_burst;
|
||||
len += cba.hta_pad;
|
||||
/* Most of the work is done in the callback. */
|
||||
if ((error = bus_dmamap_load(sc->sc_tdmatag, td->htx_dmamap,
|
||||
start, len, hme_txdma_callback, &cba, 0)) != 0 ||
|
||||
cba.hta_err != 0)
|
||||
goto fail;
|
||||
bus_dmamap_sync(sc->sc_tdmatag, td->htx_dmamap,
|
||||
BUS_DMASYNC_PREWRITE);
|
||||
|
||||
cba.hta_flags = 0;
|
||||
cba.hta_htx = td;
|
||||
if ((error = bus_dmamap_load_mbuf(sc->sc_tdmatag, td->htx_dmamap,
|
||||
m0, hme_txdma_callback, &cba, 0)) != 0)
|
||||
goto fail;
|
||||
if (cba.hta_ndescs == -1) {
|
||||
error = -1;
|
||||
goto fail;
|
||||
}
|
||||
bus_dmamap_sync(sc->sc_tdmatag, td->htx_dmamap,
|
||||
BUS_DMASYNC_PREWRITE);
|
||||
|
||||
STAILQ_REMOVE_HEAD(&sc->sc_rb.rb_txfreeq, htx_q);
|
||||
STAILQ_INSERT_TAIL(&sc->sc_rb.rb_txbusyq, td, htx_q);
|
||||
|
||||
/* Turn descriptor ownership to the hme, back to forth. */
|
||||
ri = sc->sc_rb.rb_tdhead;
|
||||
CTR2(KTR_HME, "hme_load_mbuf: next desc is %d (%#x)",
|
||||
@ -964,19 +895,7 @@ hme_load_mbuf(struct hme_softc *sc, struct mbuf *m0)
|
||||
HME_ETX_WRITE_4(sc, HME_ETXI_PENDING, HME_ETX_TP_DMAWAKEUP);
|
||||
return (0);
|
||||
fail:
|
||||
for (ri = si; ri != sc->sc_rb.rb_tdhead; ri = (ri + 1) % HME_NTXDESC) {
|
||||
td = &sc->sc_rb.rb_txdesc[ri];
|
||||
if ((td->htx_flags & HTXF_MAPPED) != 0)
|
||||
bus_dmamap_unload(sc->sc_tdmatag, td->htx_dmamap);
|
||||
td->htx_flags = 0;
|
||||
td->htx_m = NULL;
|
||||
sc->sc_rb.rb_td_nbusy--;
|
||||
HME_XD_SETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri, 0);
|
||||
}
|
||||
sc->sc_rb.rb_tdhead = si;
|
||||
error = cba.hta_err != 0 ? cba.hta_err : error;
|
||||
if (error != -1)
|
||||
device_printf(sc->sc_dev, "could not load mbuf: %d\n", error);
|
||||
bus_dmamap_unload(sc->sc_tdmatag, td->htx_dmamap);
|
||||
return (error);
|
||||
}
|
||||
|
||||
@ -988,7 +907,6 @@ hme_read(struct hme_softc *sc, int ix, int len)
|
||||
{
|
||||
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
|
||||
struct mbuf *m;
|
||||
int offs;
|
||||
|
||||
if (len <= sizeof(struct ether_header) ||
|
||||
len > ETHERMTU + sizeof(struct ether_header)) {
|
||||
@ -1002,8 +920,7 @@ hme_read(struct hme_softc *sc, int ix, int len)
|
||||
}
|
||||
|
||||
m = sc->sc_rb.rb_rxdesc[ix].hrx_m;
|
||||
offs = sc->sc_rb.rb_rxdesc[ix].hrx_offs;
|
||||
CTR2(KTR_HME, "hme_read: offs %d, len %d", offs, len);
|
||||
CTR1(KTR_HME, "hme_read: len %d", len);
|
||||
|
||||
if (hme_add_rxbuf(sc, ix, 0) != 0) {
|
||||
/*
|
||||
@ -1023,8 +940,8 @@ hme_read(struct hme_softc *sc, int ix, int len)
|
||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
||||
|
||||
m->m_pkthdr.rcvif = ifp;
|
||||
m->m_pkthdr.len = m->m_len = len + offs;
|
||||
m_adj(m, offs);
|
||||
m->m_pkthdr.len = m->m_len = len + HME_RXOFFS;
|
||||
m_adj(m, HME_RXOFFS);
|
||||
/* Pass the packet up. */
|
||||
(*ifp->if_input)(ifp, m);
|
||||
}
|
||||
@ -1045,11 +962,14 @@ hme_start(struct ifnet *ifp)
|
||||
if (m == NULL)
|
||||
break;
|
||||
|
||||
error = hme_load_mbuf(sc, m);
|
||||
if (error != 0) {
|
||||
error = hme_load_txmbuf(sc, m);
|
||||
if (error == -1) {
|
||||
ifp->if_flags |= IFF_OACTIVE;
|
||||
IF_PREPEND(&ifp->if_snd, m);
|
||||
break;
|
||||
} else if (error > 0) {
|
||||
printf("hme_start: error %d while loading mbuf\n",
|
||||
error);
|
||||
} else {
|
||||
enq = 1;
|
||||
BPF_MTAP(ifp, m);
|
||||
@ -1070,7 +990,7 @@ static void
|
||||
hme_tint(struct hme_softc *sc)
|
||||
{
|
||||
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
|
||||
struct hme_txdesc *td;
|
||||
struct hme_txdesc *htx;
|
||||
unsigned int ri, txflags;
|
||||
|
||||
/*
|
||||
@ -1090,6 +1010,7 @@ hme_tint(struct hme_softc *sc)
|
||||
HME_MAC_WRITE_4(sc, HME_MACI_EXCNT, 0);
|
||||
HME_MAC_WRITE_4(sc, HME_MACI_LTCNT, 0);
|
||||
|
||||
htx = STAILQ_FIRST(&sc->sc_rb.rb_txbusyq);
|
||||
/* Fetch current position in the transmit ring */
|
||||
for (ri = sc->sc_rb.rb_tdtail;; ri = (ri + 1) % HME_NTXDESC) {
|
||||
if (sc->sc_rb.rb_td_nbusy <= 0) {
|
||||
@ -1103,14 +1024,7 @@ hme_tint(struct hme_softc *sc)
|
||||
if ((txflags & HME_XD_OWN) != 0)
|
||||
break;
|
||||
|
||||
td = &sc->sc_rb.rb_txdesc[ri];
|
||||
CTR1(KTR_HME, "hme_tint: not owned, dflags %#x", td->htx_flags);
|
||||
if ((td->htx_flags & HTXF_MAPPED) != 0) {
|
||||
bus_dmamap_sync(sc->sc_tdmatag, td->htx_dmamap,
|
||||
BUS_DMASYNC_POSTWRITE);
|
||||
bus_dmamap_unload(sc->sc_tdmatag, td->htx_dmamap);
|
||||
}
|
||||
td->htx_flags = 0;
|
||||
CTR0(KTR_HME, "hme_tint: not owned");
|
||||
--sc->sc_rb.rb_td_nbusy;
|
||||
ifp->if_flags &= ~IFF_OACTIVE;
|
||||
|
||||
@ -1118,9 +1032,19 @@ hme_tint(struct hme_softc *sc)
|
||||
if ((txflags & HME_XD_EOP) == 0)
|
||||
continue;
|
||||
|
||||
KASSERT(htx->htx_lastdesc == ri,
|
||||
("hme_tint: ring indices skewed: %d != %d!",
|
||||
htx->htx_lastdesc, ri));
|
||||
bus_dmamap_sync(sc->sc_tdmatag, htx->htx_dmamap,
|
||||
BUS_DMASYNC_POSTWRITE);
|
||||
bus_dmamap_unload(sc->sc_tdmatag, htx->htx_dmamap);
|
||||
|
||||
ifp->if_opackets++;
|
||||
m_freem(td->htx_m);
|
||||
td->htx_m = NULL;
|
||||
m_freem(htx->htx_m);
|
||||
htx->htx_m = NULL;
|
||||
STAILQ_REMOVE_HEAD(&sc->sc_rb.rb_txbusyq, htx_q);
|
||||
STAILQ_INSERT_TAIL(&sc->sc_rb.rb_txfreeq, htx, htx_q);
|
||||
htx = STAILQ_FIRST(&sc->sc_rb.rb_txbusyq);
|
||||
}
|
||||
/* Turn off watchdog */
|
||||
if (sc->sc_rb.rb_td_nbusy == 0)
|
||||
@ -1393,7 +1317,6 @@ hme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
|
||||
* Reset the interface to pick up changes in any other
|
||||
* flags that affect hardware registers.
|
||||
*/
|
||||
/*hme_stop(sc);*/
|
||||
hme_init(sc);
|
||||
}
|
||||
#ifdef HMEDEBUG
|
||||
|
||||
@ -304,3 +304,6 @@
|
||||
(((flags) & HME_XD_TXLENMSK) >> 0)
|
||||
|
||||
#define PCI_HME_BASEADDR 0x10
|
||||
|
||||
#define HME_MINRXALIGN 0x10
|
||||
#define HME_RXOFFS 2
|
||||
|
||||
@ -45,12 +45,15 @@
|
||||
* an mbuf cluster is allocated and set up to receive a packet, and a dma map
|
||||
* is created. Therefore, this number should not be too high to not waste
|
||||
* memory.
|
||||
* TX descriptors have less static cost (a dma map is allocated which could
|
||||
* cause bounce buffers to be reserved; other that that, the only required
|
||||
* memory is sizeof(struct hme_txdesc)).
|
||||
* TX descriptors have no static cost, except for the memory directly allocated
|
||||
* for them. TX queue elements (the number of which is fixed by HME_NTXQ) hold
|
||||
* the software state for a transmit job; each has a dmamap allocated for it.
|
||||
* There may be multiple descriptors allocated to a single queue element.
|
||||
* HME_NTXQ is completely arbitrary.
|
||||
*/
|
||||
#define HME_NRXDESC 128
|
||||
#define HME_NTXDESC 64
|
||||
#define HME_NTXDESC 128
|
||||
#define HME_NTXQ (HME_NTXDESC / 2)
|
||||
|
||||
/* Maximum size of a mapped RX buffer. */
|
||||
#define HME_BUFSZ 1600
|
||||
@ -62,16 +65,21 @@
|
||||
struct hme_rxdesc {
|
||||
struct mbuf *hrx_m;
|
||||
bus_dmamap_t hrx_dmamap;
|
||||
int hrx_offs;
|
||||
bus_size_t hrx_len;
|
||||
};
|
||||
|
||||
/* Lazily leave at least one burst size grace space. */
|
||||
#define HME_DESC_RXLEN(sc, d) \
|
||||
ulmin(HME_BUFSZ, (d)->hrx_m->m_len - (sc)->sc_burst)
|
||||
|
||||
struct hme_txdesc {
|
||||
struct mbuf *htx_m;
|
||||
bus_dmamap_t htx_dmamap;
|
||||
int htx_flags;
|
||||
int htx_lastdesc;
|
||||
STAILQ_ENTRY(hme_txdesc) htx_q;
|
||||
};
|
||||
|
||||
STAILQ_HEAD(hme_txdq, hme_txdesc);
|
||||
|
||||
/* Value for htx_flags */
|
||||
#define HTXF_MAPPED 1
|
||||
|
||||
@ -85,13 +93,16 @@ struct hme_ring {
|
||||
bus_addr_t rb_rxddma; /* DMA address of same */
|
||||
|
||||
/* Ring Descriptor state */
|
||||
int rb_tdhead, rb_tdtail;
|
||||
int rb_rdtail;
|
||||
int rb_td_nbusy;
|
||||
int rb_tdhead, rb_tdtail;
|
||||
int rb_rdtail;
|
||||
int rb_td_nbusy;
|
||||
|
||||
/* Descriptors */
|
||||
struct hme_rxdesc rb_rxdesc[HME_NRXDESC];
|
||||
struct hme_txdesc rb_txdesc[HME_NTXDESC];
|
||||
struct hme_rxdesc rb_rxdesc[HME_NRXDESC];
|
||||
struct hme_txdesc rb_txdesc[HME_NTXQ];
|
||||
|
||||
struct hme_txdq rb_txfreeq;
|
||||
struct hme_txdq rb_txbusyq;
|
||||
|
||||
bus_dmamap_t rb_spare_dmamap;
|
||||
};
|
||||
@ -134,10 +145,6 @@ struct hme_softc {
|
||||
struct hme_ring sc_rb;
|
||||
|
||||
int sc_debug;
|
||||
|
||||
/* Special hardware hooks */
|
||||
void (*sc_hwreset)(struct hme_softc *);
|
||||
void (*sc_hwinit)(struct hme_softc *);
|
||||
};
|
||||
|
||||
extern devclass_t hme_devclass;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user