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Code Issues Releases Activity

Do the cache invalidate sequence from the outermost to innermost, required

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for correct operation.

Submitted by:	Michal Meloun <meloun@miracle.cz>
This commit is contained in:
Ian Lepore 2014-11-16 20:59:27 +00:00
parent f5b11228ad
commit 1c716437d5
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=274603
1 changed files with 1 additions and 1 deletions
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2
sys/arm/arm/busdma_machdep-v6.c
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@ -1372,8 +1372,8 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
len = (len -
(len & arm_dcache_align_mask)) +
arm_dcache_align;
cpu_dcache_inv_range(startv, len);
l2cache_inv_range(startv, startp, len);
cpu_dcache_inv_range(startv, len);
if (bpage->datavaddr != 0)
bcopy((void *)bpage->vaddr,
(void *)bpage->datavaddr,