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Mdoc(7) janitor cleanup.
Reviewed and improved by: ru OK'ed by: phk Approved by: re (rwatson)
This commit is contained in:
Simon L. B. Nielsen
parent
320a3e0c19
commit
1cd908be33
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=123059
@ -1,4 +1,4 @@
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.\" Copyright (c) 2003 Poul-Henning Kamp <phk@FreeBSD.org>
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.\" Copyright (c) 2003 Poul-Henning Kamp <phk@FreeBSD.org>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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@ -25,87 +25,134 @@
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.\" $FreeBSD$
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.\"
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.Dd November 23, 2003
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.Dt CPU_ELAN 4
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.Dt CPU_ELAN 4 i386
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.Os
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.Sh NAME
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.Nm CPU_ELAN
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.Nd AMD Elan 520 CPU support
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.Sh SYNOPSIS
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.Cd options CPU_ELAN
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.Cd options CPU_ELAN_PPS
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.Cd options CPU_ELAN_XTAL
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.Cd sysctl machdep.elan_gpio_config
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.Cd sysctl machdep.elan_freq
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.Cd options CPU_SOEKRIS
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.Cd "options CPU_ELAN"
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.Cd "options CPU_ELAN_PPS"
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.Cd "options CPU_ELAN_XTAL"
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.Bl -item -compact
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.It
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.Va machdep.elan_gpio_config
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.It
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.Va machdep.elan_freq
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.El
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.Cd "options CPU_SOEKRIS"
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.Sh DESCRIPTION
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.Cd options CPU_ELAN
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Enables support for the AMD Elan 520 CPU.
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The
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.Cd "options CPU_ELAN"
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enables support for the AMD Elan 520 CPU.
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.Pp
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A device "/dev/elan-mmcr" exports the MMCR register bank to userland
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A device
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.Pa /dev/elan-mmcr
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exports the MMCR register bank to userland
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using
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.Xr mmap 2 .
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.Pp
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The "i8254" timer will be adjusted to the slightly unorthodox
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frequency 1189161Hz (32768 * 45 * 25 / 31) employed by the Elan.
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The
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.Tn i8254
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timer will be adjusted to the slightly unorthodox
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frequency 1189161 Hz (32768 * 45 * 25 / 31) employed by the Elan.
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.Pp
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A timecounter named "ELAN" is implemented using the general purpose timer 2,
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A timecounter named
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.Dq Li ELAN
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is implemented using the general purpose timer 2,
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but it will not be usable unless HZ is configured at 150 or higher.
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This timecounter is much better than the "i8254" timecounter and should be
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This timecounter is much better than the
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.Dq Li i8254
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timecounter and should be
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used at all times.
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.Pp
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The
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.Cd sysctl machdep.elan_gpio_config
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.Va machdep.elan_gpio_config
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.Xr sysctl 8
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variable
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enables configuration of the GPIO pins of the CPU.
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The string must be exactly 32 characters long.
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A '-' means the GPIO is unavailable.
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A 'l' (lower-case L) configures a
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A
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.Ql -
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means the GPIO is unavailable.
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A
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.Ql l
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(lower-case ell) configures a
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.Xr led 4
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device (active low).
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A 'L' configures a
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A
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.Ql L
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configures a
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.Xr led 4
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device (active higH).
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A '.' means no configuration for this GPIO.
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device (active high).
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A
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.Ql \&.
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means no configuration for this GPIO.
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These
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.Xr led 4
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devices will be named "/dev/led/gpio%d".
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For meaning of 'P', 'e' and 'E', see under
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.Cd options CPU_ELAN_PPS .
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devices will be named
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.Pa /dev/led/gpio%d .
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For meaning of
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.Ql P ,
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.Ql e
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and
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.Ql E ,
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see under
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.Cd "options CPU_ELAN_PPS" .
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.Pp
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The
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.Cd options CPU_ELAN_XTAL
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and
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.Cd sysctl machdep.elan_freq
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.Cd "options CPU_ELAN_XTAL"
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and the
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.Va machdep.elan_freq
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.Xr sysctl 8
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variable
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can be used to set the CPU clock crystal frequency in Hz.
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The default is 33333333 Hz.
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.Pp
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The
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.Cd options CPU_ELAN_PPS
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.Cd "options CPU_ELAN_PPS"
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enables precision timestamping using the RFC2783 PPS-API via the
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"/dev/elan-mmcr" device.
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The resolution will be approx 125nsec and the precision \(+- 125nsec.
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(for 125 nsec read "4 / CPU clock crystal frequency")
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.Pa /dev/elan-mmcr
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device.
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The resolution will be approximately 125 nsec
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and the precision \(+- 125 nsec.
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(For 125 nsec read
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.Dq "4 / CPU clock crystal frequency" . )
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.Pp
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The input signal must be connected to the TMR1IN pin and
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a GPIO pin.
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The GPIO pin must be configured with a 'P' in
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.Cd sysctl machdep.elan_gpio_config .
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The GPIO pin must be configured with a
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.Ql P
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in
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.Va machdep.elan_gpio_config .
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.Pp
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In addition one GPIO pin can be configured with either 'e' (active low)
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or 'E' (active high) to become a "echo" output of the input signal.
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In addition, one GPIO pin can be configured with either
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.Ql e
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(active low)
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or
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.Ql E
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(active high) to become a
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.Dq echo
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output of the input signal.
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Please notice that this signal is not suitable for calibration.
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.Pp
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If the
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.Cd options CPU_SOEKRIS
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option is given, the support will additionally be tailored to the
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.Cd "options CPU_SOEKRIS"
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is given, the support will additionally be tailored to the
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Soekris Engineering 45xx series of embedded computers.
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The "error" led will be configured (as "/dev/led/error") and the GPIO pins which are not
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The
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.Dq error
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led will be configured (as
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.Pa /dev/led/error )
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and the GPIO pins which are not
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available will be disabled.
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.Sh SEE ALSO
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.Xr sysctl 8 ,
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.Xr led 4 ,
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.Xr sysctl 8
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.Sh HISTORY
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The
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.Nm
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code first appeared in
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.Fx 5.x .
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.Fx 4.7 .
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.Sh AUTHORS
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.An "Poul-Henning Kamp" Aq phk@FreeBSD.org
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