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synced 2025-01-29 16:44:03 +00:00
Cleanup address range checks in ioat(4).
- Deduce allowed address range for bus_dma(9) from the hardware version. Different versions (CPU generations) have different documented limits. - Remove difference between address ranges for src/dst and crc. At least docs for few recent generations of CPUs do not mention anything like that, while older are already limited with above limits. - Remove address assertions from arguments. While I do not think the addresses out of allowed ranges should realistically happen there due to the platforms physical address limitations, there is now bus_dma(9) to make sure of that, preferably via IOMMU. - Since crc now has the same address range as src/dst, remove crc_dmamap, reusing dst2_dmamap instead. Discussed with: cem MFC after: 2 weeks Sponsored by: iXsystems, Inc.
This commit is contained in:
Alexander Motin
parent
b141dd5ddf
commit
1f4a469d36
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=354752
@ -64,7 +64,10 @@ __FBSDID("$FreeBSD$");
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#include "ioat_internal.h"
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#ifndef BUS_SPACE_MAXADDR_40BIT
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#define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL
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#define BUS_SPACE_MAXADDR_40BIT MIN(BUS_SPACE_MAXADDR, 0xFFFFFFFFFFULL)
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#endif
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#ifndef BUS_SPACE_MAXADDR_46BIT
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#define BUS_SPACE_MAXADDR_46BIT MIN(BUS_SPACE_MAXADDR, 0x3FFFFFFFFFFFULL)
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#endif
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static int ioat_probe(device_t device);
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@ -413,17 +416,6 @@ ioat_detach(device_t device)
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bus_dma_tag_destroy(ioat->data_tag);
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}
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if (ioat->data_crc_tag != NULL) {
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for (i = 0; i < 1 << ioat->ring_size_order; i++) {
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error = ioat_bus_dmamap_destroy(ioat, __func__,
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ioat->data_crc_tag, ioat->ring[i].crc_dmamap);
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if (error != 0)
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return (error);
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}
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bus_dma_tag_destroy(ioat->data_crc_tag);
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}
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if (ioat->ring != NULL)
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ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring);
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@ -514,6 +506,7 @@ ioat3_attach(device_t device)
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struct ioat_descriptor *ring;
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struct ioat_dma_hw_descriptor *dma_hw_desc;
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void *hw_desc;
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bus_addr_t lowaddr;
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size_t ringsz;
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int i, num_descriptors;
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int error;
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@ -549,16 +542,25 @@ ioat3_attach(device_t device)
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ioat->is_submitter_processing = FALSE;
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bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0,
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BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
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if (ioat->version >= IOAT_VER_3_3)
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lowaddr = BUS_SPACE_MAXADDR_48BIT;
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else if (ioat->version >= IOAT_VER_3_2)
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lowaddr = BUS_SPACE_MAXADDR_46BIT;
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else
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lowaddr = BUS_SPACE_MAXADDR_40BIT;
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error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
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sizeof(uint64_t), 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
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sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL,
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&ioat->comp_update_tag);
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if (error != 0)
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return (error);
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error = bus_dmamem_alloc(ioat->comp_update_tag,
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(void **)&ioat->comp_update, BUS_DMA_ZERO | BUS_DMA_WAITOK,
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&ioat->comp_update_map);
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if (ioat->comp_update == NULL)
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return (ENOMEM);
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if (error != 0)
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return (error);
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error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map,
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ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat,
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@ -571,9 +573,8 @@ ioat3_attach(device_t device)
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ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors;
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error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
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2 * 1024 * 1024, 0x0, (bus_addr_t)BUS_SPACE_MAXADDR_40BIT,
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BUS_SPACE_MAXADDR, NULL, NULL, ringsz, 1, ringsz, 0, NULL, NULL,
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&ioat->hw_desc_tag);
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2 * 1024 * 1024, 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
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ringsz, 1, ringsz, 0, NULL, NULL, &ioat->hw_desc_tag);
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if (error != 0)
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return (error);
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@ -590,24 +591,11 @@ ioat3_attach(device_t device)
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ioat->hw_desc_ring = hw_desc;
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error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
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1, 0, BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL,
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ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL,
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&ioat->data_crc_tag);
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if (error != 0) {
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ioat_log_message(0, "%s: bus_dma_tag_create failed %d\n",
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__func__, error);
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return (error);
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}
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error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
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1, 0, BUS_SPACE_MAXADDR_48BIT, BUS_SPACE_MAXADDR, NULL, NULL,
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1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
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ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL,
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&ioat->data_tag);
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if (error != 0) {
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ioat_log_message(0, "%s: bus_dma_tag_create failed %d\n",
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__func__, error);
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if (error != 0)
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return (error);
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}
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ioat->ring = malloc_domainset(num_descriptors * sizeof(*ring), M_IOAT,
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DOMAINSET_PREF(ioat->domain), M_ZERO | M_WAITOK);
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@ -647,14 +635,6 @@ ioat3_attach(device_t device)
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error);
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return (error);
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}
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error = bus_dmamap_create(ioat->data_crc_tag, 0,
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&ring[i].crc_dmamap);
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if (error != 0) {
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ioat_log_message(0,
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"%s: bus_dmamap_create failed %d\n", __func__,
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error);
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return (error);
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}
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}
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for (i = 0; i < num_descriptors; i++) {
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@ -853,7 +833,6 @@ ioat_process_events(struct ioat_softc *ioat, boolean_t intr)
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bus_dmamap_unload(ioat->data_tag, desc->dst_dmamap);
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bus_dmamap_unload(ioat->data_tag, desc->src2_dmamap);
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bus_dmamap_unload(ioat->data_tag, desc->dst2_dmamap);
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bus_dmamap_unload(ioat->data_crc_tag, desc->crc_dmamap);
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if (dmadesc->callback_fn != NULL)
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dmadesc->callback_fn(dmadesc->callback_arg, 0);
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@ -1223,10 +1202,6 @@ ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
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struct ioat_softc *ioat;
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ioat = to_ioat_softc(dmaengine);
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KASSERT(((src | dst) & (0xffffull << 48)) == 0,
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("%s: high 16 bits of src/dst are not zero", __func__));
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desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn,
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callback_arg, flags);
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if (desc == NULL)
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@ -1257,8 +1232,6 @@ ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1,
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ioat = to_ioat_softc(dmaengine);
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CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
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KASSERT(((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) == 0,
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("%s: high 16 bits of src/dst are not zero", __func__));
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KASSERT(((src1 | src2 | dst1 | dst2) & PAGE_MASK) == 0,
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("%s: addresses are not page-aligned", __func__));
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@ -1340,8 +1313,6 @@ ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
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KASSERT((ioat->capabilities & IOAT_DMACAP_MOVECRC) != 0,
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("%s: device lacks MOVECRC capability", __func__));
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KASSERT(((src | dst) & (0xffffffull << 40)) == 0,
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("%s: high 24 bits of src/dst are not zero", __func__));
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teststore = (flags & _DMA_CRC_TESTSTORE);
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KASSERT(teststore != _DMA_CRC_TESTSTORE,
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("%s: TEST and STORE invalid", __func__));
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@ -1361,10 +1332,6 @@ ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
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break;
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}
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KASSERT((flags & DMA_CRC_INLINE) != 0 ||
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(crcptr & (0xffffffull << 40)) == 0,
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("%s: high 24 bits of crcptr are not zero", __func__));
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desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn,
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callback_arg, flags & ~_DMA_CRC_FLAGS);
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if (desc == NULL)
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@ -1374,8 +1341,8 @@ ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
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if ((flags & DMA_CRC_INLINE) == 0) {
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nseg = -1;
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error = _bus_dmamap_load_phys(ioat->data_crc_tag,
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desc->crc_dmamap, crcptr, sizeof(uint32_t), 0,
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error = _bus_dmamap_load_phys(ioat->data_tag,
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desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0,
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&seg, &nseg);
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if (error != 0) {
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ioat_log_message(0, "%s: _bus_dmamap_load_phys"
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@ -1416,8 +1383,6 @@ ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
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KASSERT((ioat->capabilities & IOAT_DMACAP_CRC) != 0,
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("%s: device lacks CRC capability", __func__));
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KASSERT((src & (0xffffffull << 40)) == 0,
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("%s: high 24 bits of src are not zero", __func__));
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teststore = (flags & _DMA_CRC_TESTSTORE);
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KASSERT(teststore != _DMA_CRC_TESTSTORE,
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("%s: TEST and STORE invalid", __func__));
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@ -1437,10 +1402,6 @@ ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
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break;
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}
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KASSERT((flags & DMA_CRC_INLINE) != 0 ||
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(crcptr & (0xffffffull << 40)) == 0,
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("%s: high 24 bits of crcptr are not zero", __func__));
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desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn,
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callback_arg, flags & ~_DMA_CRC_FLAGS);
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if (desc == NULL)
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@ -1450,8 +1411,8 @@ ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
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if ((flags & DMA_CRC_INLINE) == 0) {
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nseg = -1;
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error = _bus_dmamap_load_phys(ioat->data_crc_tag,
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desc->crc_dmamap, crcptr, sizeof(uint32_t), 0,
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error = _bus_dmamap_load_phys(ioat->data_tag,
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desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0,
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&seg, &nseg);
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if (error != 0) {
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ioat_log_message(0, "%s: _bus_dmamap_load_phys"
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@ -1488,8 +1449,6 @@ ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern,
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KASSERT((ioat->capabilities & IOAT_DMACAP_BFILL) != 0,
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("%s: device lacks BFILL capability", __func__));
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KASSERT((dst & (0xffffull << 48)) == 0,
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("%s: high 16 bits of crcptr are not zero", __func__));
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desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, 0, dst,
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callback_fn, callback_arg, flags);
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@ -418,7 +418,6 @@ struct ioat_descriptor {
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bus_dmamap_t dst_dmamap;
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bus_dmamap_t src2_dmamap;
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bus_dmamap_t dst2_dmamap;
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bus_dmamap_t crc_dmamap;
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};
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/* Unused by this driver at this time. */
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@ -465,7 +464,6 @@ struct ioat_softc {
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bus_dmamap_t hw_desc_map;
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bus_dma_tag_t data_tag;
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bus_dma_tag_t data_crc_tag;
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bus_dma_tag_t comp_update_tag;
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bus_dmamap_t comp_update_map;
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