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add TBTT interrupt support; this was added in Griffin so consumers should
check HAL_CAP_INTRMASK before using it NB: didn't test 11n parts yet so supported only for 5212-class parts
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parent
00e602a997
commit
210411e0f1
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=192400
@ -335,6 +335,7 @@ typedef enum {
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HAL_INT_GPIO = 0x01000000,
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HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
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HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
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HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
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HAL_INT_CST = 0x10000000, /* Non-common mapping */
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HAL_INT_GTT = 0x20000000, /* Non-common mapping */
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HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
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@ -342,7 +343,8 @@ typedef enum {
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HAL_INT_BMISC = HAL_INT_TIM
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| HAL_INT_DTIM
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| HAL_INT_DTIMSYNC
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| HAL_INT_CABEND,
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| HAL_INT_CABEND
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| HAL_INT_TBTT,
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/* Interrupt bits that map directly to ISR/IMR bits */
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HAL_INT_COMMON = HAL_INT_RXNOFRM
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@ -847,6 +847,8 @@ ar5212FillCapabilityInfo(struct ath_hal *ah)
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| HAL_INT_BNR
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| HAL_INT_BMISC
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;
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if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)
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pCap->halIntrMask &= ~HAL_INT_TBTT;
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return AH_TRUE;
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#undef IS_COBRA
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@ -70,6 +70,8 @@ ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
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mask2 |= HAL_INT_DTIMSYNC;
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if (isr2 & AR_ISR_S2_CABEND)
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mask2 |= HAL_INT_CABEND;
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if (isr2 & AR_ISR_S2_TBTT)
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mask2 |= HAL_INT_TBTT;
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}
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isr = OS_REG_READ(ah, AR_ISR_RAC);
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if (isr == 0xffffffff) {
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@ -172,6 +174,8 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
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mask2 |= AR_IMR_S2_DTIMSYNC;
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if (ints & HAL_INT_CABEND)
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mask2 |= AR_IMR_S2_CABEND;
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if (ints & HAL_INT_TBTT)
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mask2 |= AR_IMR_S2_TBTT;
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}
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if (ints & HAL_INT_FATAL) {
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/*
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@ -463,7 +463,8 @@
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#define AR_ISR_S2_BCNTO 0x08000000 /* BCNTO */
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#define AR_ISR_S2_CABTO 0x10000000 /* CABTO */
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#define AR_ISR_S2_DTIM 0x20000000 /* DTIM */
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#define AR_ISR_S2_RESV0 0xE0F8FC00 /* Reserved */
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#define AR_ISR_S2_TSFOOR 0x40000000 /* TSF OOR */
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#define AR_ISR_S2_TBTT 0x80000000 /* TBTT timer */
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#define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
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#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
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@ -531,13 +532,14 @@
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#define AR_IMR_S2_BCNTO 0x08000000 /* BCNTO */
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#define AR_IMR_S2_CABTO 0x10000000 /* CABTO */
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#define AR_IMR_S2_DTIM 0x20000000 /* DTIM */
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#define AR_IMR_S2_TSFOOR 0x80000000 /* TSF OOR */
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#define AR_IMR_S2_RESV0 0xE0F8FC00 /* Reserved */
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#define AR_IMR_S2_TSFOOR 0x40000000 /* TSF OOR */
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#define AR_IMR_S2_TBTT 0x80000000 /* TBTT timer */
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/* AR_IMR_SR2 bits that correspond to AR_IMR_BCNMISC */
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#define AR_IMR_SR2_BCNMISC \
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(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | \
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AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR)
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AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR | \
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AR_IMR_S2_TBTT)
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#define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
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#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
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