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- When creating the DMA tag for user data, don't ask for more segments
than required for handling MAXPHYS and report the resulting maximum I/O size to CAM instead of implicitly limiting it to DFLTPHYS. - Move the variables of sym_action2() out of nested scope as required by style(9) and remove extraneous curly braces. - Replace a magic value for PCIR_COMMAND with the appropriate macro. - Use DEVMETHOD_END. - Use NULL instead of 0 for pointers. Tested with a HBA donated by wilko. MFC after: 3 days
This commit is contained in:
parent
2dbc3019d0
commit
21b5913f1f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=236061
@ -82,6 +82,13 @@
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*/
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*/
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#define SYM_CONF_MAX_TAG_ORDER (6)
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#define SYM_CONF_MAX_TAG_ORDER (6)
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/*
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* DMA boundary
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* We need to ensure 16 MB boundaries not to be crossed during DMA of
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* each segment, due to some chips being flawed.
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*/
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#define SYM_CONF_DMA_BOUNDARY (1UL << 24)
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/*
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/*
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* Max number of scatter/gather entries for en IO.
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* Max number of scatter/gather entries for en IO.
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* Each entry costs 8 bytes in the internal CCB data structure.
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* Each entry costs 8 bytes in the internal CCB data structure.
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@ -1623,6 +1623,7 @@ struct sym_hcb {
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u_int features; /* Chip features map */
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u_int features; /* Chip features map */
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u_char myaddr; /* SCSI id of the adapter */
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u_char myaddr; /* SCSI id of the adapter */
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u_char maxburst; /* log base 2 of dwords burst */
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u_char maxburst; /* log base 2 of dwords burst */
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u_char maxsegcnt; /* Max DMA S/G segments */
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u_char maxwide; /* Maximum transfer width */
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u_char maxwide; /* Maximum transfer width */
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u_char minsync; /* Min sync period factor (ST) */
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u_char minsync; /* Min sync period factor (ST) */
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u_char maxsync; /* Max sync period factor (ST) */
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u_char maxsync; /* Max sync period factor (ST) */
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@ -7988,10 +7989,7 @@ sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp,
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/*
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/*
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* Scatter a SG list with physical addresses into bus addressable chunks.
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* Scatter a SG list with physical addresses into bus addressable chunks.
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* We need to ensure 16MB boundaries not to be crossed during DMA of
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* each segment, due to some chips being flawed.
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*/
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*/
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#define BOUND_MASK ((1UL<<24)-1)
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static int
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static int
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sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs)
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sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs)
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{
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{
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@ -8007,7 +8005,7 @@ sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs)
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pe = ps + psegs[t].ds_len;
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pe = ps + psegs[t].ds_len;
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while (s >= 0) {
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while (s >= 0) {
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pn = (pe - 1) & ~BOUND_MASK;
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pn = (pe - 1) & ~(SYM_CONF_DMA_BOUNDARY - 1);
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if (pn <= ps)
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if (pn <= ps)
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pn = ps;
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pn = ps;
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k = pe - pn;
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k = pe - pn;
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@ -8032,17 +8030,21 @@ sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs)
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return t >= 0 ? -1 : 0;
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return t >= 0 ? -1 : 0;
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}
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}
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#undef BOUND_MASK
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/*
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/*
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* SIM action for non performance critical stuff.
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* SIM action for non performance critical stuff.
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*/
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*/
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static void sym_action2(struct cam_sim *sim, union ccb *ccb)
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static void sym_action2(struct cam_sim *sim, union ccb *ccb)
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{
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{
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union ccb *abort_ccb;
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struct ccb_hdr *ccb_h;
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struct ccb_pathinq *cpi;
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struct ccb_trans_settings *cts;
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struct sym_trans *tip;
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hcb_p np;
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hcb_p np;
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tcb_p tp;
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tcb_p tp;
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lcb_p lp;
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lcb_p lp;
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struct ccb_hdr *ccb_h;
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u_char dflags;
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/*
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/*
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* Retrieve our controller data structure.
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* Retrieve our controller data structure.
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@ -8055,9 +8057,6 @@ static void sym_action2(struct cam_sim *sim, union ccb *ccb)
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switch (ccb_h->func_code) {
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switch (ccb_h->func_code) {
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case XPT_SET_TRAN_SETTINGS:
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case XPT_SET_TRAN_SETTINGS:
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{
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struct ccb_trans_settings *cts;
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cts = &ccb->cts;
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cts = &ccb->cts;
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tp = &np->target[ccb_h->target_id];
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tp = &np->target[ccb_h->target_id];
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@ -8079,13 +8078,7 @@ static void sym_action2(struct cam_sim *sim, union ccb *ccb)
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sym_xpt_done2(np, ccb, CAM_REQ_CMP);
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sym_xpt_done2(np, ccb, CAM_REQ_CMP);
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break;
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break;
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}
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case XPT_GET_TRAN_SETTINGS:
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case XPT_GET_TRAN_SETTINGS:
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{
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struct ccb_trans_settings *cts;
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struct sym_trans *tip;
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u_char dflags;
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cts = &ccb->cts;
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cts = &ccb->cts;
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tp = &np->target[ccb_h->target_id];
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tp = &np->target[ccb_h->target_id];
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lp = sym_lp(np, tp, ccb_h->target_lun);
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lp = sym_lp(np, tp, ccb_h->target_lun);
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@ -8129,16 +8122,12 @@ static void sym_action2(struct cam_sim *sim, union ccb *ccb)
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#undef cts__scsi
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#undef cts__scsi
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sym_xpt_done2(np, ccb, CAM_REQ_CMP);
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sym_xpt_done2(np, ccb, CAM_REQ_CMP);
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break;
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break;
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}
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case XPT_CALC_GEOMETRY:
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case XPT_CALC_GEOMETRY:
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{
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cam_calc_geometry(&ccb->ccg, /*extended*/1);
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cam_calc_geometry(&ccb->ccg, /*extended*/1);
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sym_xpt_done2(np, ccb, CAM_REQ_CMP);
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sym_xpt_done2(np, ccb, CAM_REQ_CMP);
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break;
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break;
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}
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case XPT_PATH_INQ:
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case XPT_PATH_INQ:
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{
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cpi = &ccb->cpi;
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struct ccb_pathinq *cpi = &ccb->cpi;
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cpi->version_num = 1;
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cpi->version_num = 1;
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cpi->hba_inquiry = PI_MDP_ABLE|PI_SDTR_ABLE|PI_TAG_ABLE;
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cpi->hba_inquiry = PI_MDP_ABLE|PI_SDTR_ABLE|PI_TAG_ABLE;
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if ((np->features & FE_WIDE) != 0)
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if ((np->features & FE_WIDE) != 0)
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@ -8173,12 +8162,11 @@ static void sym_action2(struct cam_sim *sim, union ccb *ccb)
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cpi->xport_specific.spi.ppr_options =
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cpi->xport_specific.spi.ppr_options =
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SID_SPI_CLOCK_DT_ST;
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SID_SPI_CLOCK_DT_ST;
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}
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}
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cpi->maxio = np->maxsegcnt * SYM_CONF_DMA_BOUNDARY;
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sym_xpt_done2(np, ccb, CAM_REQ_CMP);
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sym_xpt_done2(np, ccb, CAM_REQ_CMP);
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break;
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break;
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}
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case XPT_ABORT:
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case XPT_ABORT:
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{
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abort_ccb = ccb->cab.abort_ccb;
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union ccb *abort_ccb = ccb->cab.abort_ccb;
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switch(abort_ccb->ccb_h.func_code) {
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switch(abort_ccb->ccb_h.func_code) {
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case XPT_SCSI_IO:
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case XPT_SCSI_IO:
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if (sym_abort_scsiio(np, abort_ccb, 0) == 0) {
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if (sym_abort_scsiio(np, abort_ccb, 0) == 0) {
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@ -8190,14 +8178,10 @@ static void sym_action2(struct cam_sim *sim, union ccb *ccb)
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break;
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break;
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}
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}
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break;
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break;
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}
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case XPT_RESET_DEV:
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case XPT_RESET_DEV:
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{
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sym_reset_dev(np, ccb);
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sym_reset_dev(np, ccb);
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break;
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break;
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}
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case XPT_RESET_BUS:
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case XPT_RESET_BUS:
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{
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sym_reset_scsi_bus(np, 0);
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sym_reset_scsi_bus(np, 0);
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if (sym_verbose) {
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if (sym_verbose) {
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xpt_print_path(np->path);
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xpt_print_path(np->path);
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@ -8206,7 +8190,6 @@ static void sym_action2(struct cam_sim *sim, union ccb *ccb)
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sym_init (np, 1);
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sym_init (np, 1);
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sym_xpt_done2(np, ccb, CAM_REQ_CMP);
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sym_xpt_done2(np, ccb, CAM_REQ_CMP);
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break;
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break;
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}
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case XPT_ACCEPT_TARGET_IO:
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case XPT_ACCEPT_TARGET_IO:
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case XPT_CONT_TARGET_IO:
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case XPT_CONT_TARGET_IO:
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case XPT_EN_LUN:
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case XPT_EN_LUN:
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@ -8362,7 +8345,7 @@ sym_update_dflags(hcb_p np, u_char *flags, struct ccb_trans_settings *cts)
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static device_method_t sym_pci_methods[] = {
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static device_method_t sym_pci_methods[] = {
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DEVMETHOD(device_probe, sym_pci_probe),
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DEVMETHOD(device_probe, sym_pci_probe),
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DEVMETHOD(device_attach, sym_pci_attach),
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DEVMETHOD(device_attach, sym_pci_attach),
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{ 0, 0 }
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DEVMETHOD_END
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};
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};
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static driver_t sym_pci_driver = {
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static driver_t sym_pci_driver = {
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@ -8373,7 +8356,7 @@ static driver_t sym_pci_driver = {
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static devclass_t sym_devclass;
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static devclass_t sym_devclass;
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DRIVER_MODULE(sym, pci, sym_pci_driver, sym_devclass, 0, 0);
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DRIVER_MODULE(sym, pci, sym_pci_driver, sym_devclass, NULL, NULL);
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MODULE_DEPEND(sym, cam, 1, 1, 1);
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MODULE_DEPEND(sym, cam, 1, 1, 1);
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MODULE_DEPEND(sym, pci, 1, 1, 1);
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MODULE_DEPEND(sym, pci, 1, 1, 1);
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@ -8586,15 +8569,16 @@ sym_pci_attach(device_t dev)
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/*
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/*
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* Allocate a tag for the DMA of user data.
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* Allocate a tag for the DMA of user data.
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*/
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*/
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if (bus_dma_tag_create(np->bus_dmat, 1, (1<<24),
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np->maxsegcnt = MIN(SYM_CONF_MAX_SG,
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BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
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(MAXPHYS / SYM_CONF_DMA_BOUNDARY) + 1);
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NULL, NULL,
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if (bus_dma_tag_create(np->bus_dmat, 1, SYM_CONF_DMA_BOUNDARY,
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BUS_SPACE_MAXSIZE, SYM_CONF_MAX_SG,
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BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
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(1<<24), 0, busdma_lock_mutex, &np->mtx,
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BUS_SPACE_MAXSIZE, np->maxsegcnt, SYM_CONF_DMA_BOUNDARY,
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&np->data_dmat)) {
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BUS_DMA_ALLOCNOW, busdma_lock_mutex, &np->mtx, &np->data_dmat)) {
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device_printf(dev, "failed to create DMA tag.\n");
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device_printf(dev, "failed to create DMA tag.\n");
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goto attach_failed;
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goto attach_failed;
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}
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}
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/*
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/*
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* Read and apply some fix-ups to the PCI COMMAND
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* Read and apply some fix-ups to the PCI COMMAND
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* register. We want the chip to be enabled for:
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* register. We want the chip to be enabled for:
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@ -8603,9 +8587,8 @@ sym_pci_attach(device_t dev)
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* - Write And Invalidate.
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* - Write And Invalidate.
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*/
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*/
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command = pci_read_config(dev, PCIR_COMMAND, 2);
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command = pci_read_config(dev, PCIR_COMMAND, 2);
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command |= PCIM_CMD_BUSMASTEREN;
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command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_PERRESPEN |
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command |= PCIM_CMD_PERRESPEN;
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PCIM_CMD_MWRICEN;
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command |= /* PCIM_CMD_MWIEN */ 0x0010;
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pci_write_config(dev, PCIR_COMMAND, command, 2);
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pci_write_config(dev, PCIR_COMMAND, command, 2);
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/*
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/*
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