mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-21 11:13:30 +00:00
MF p4:
Adapt to forthcoming spi framework. The ioctls for SPI commands and such belong in the higher level driver.
This commit is contained in:
Warner Losh
parent
567314271b
commit
21caaf799a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=160358
@ -39,7 +39,10 @@ __FBSDID("$FreeBSD$");
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#include <machine/bus.h>
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#include <arm/at91/at91_spireg.h>
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#include <arm/at91/at91_spiio.h>
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#include <arm/at91/at91_pdcreg.h>
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#include <dev/spibus/spi.h>
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#include "spibus_if.h"
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struct at91_spi_softc
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{
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@ -48,13 +51,8 @@ struct at91_spi_softc
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struct resource *irq_res; /* IRQ resource */
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struct resource *mem_res; /* Memory resource */
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struct mtx sc_mtx; /* basically a perimeter lock */
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int flags;
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#define XFER_PENDING 1 /* true when transfer taking place */
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#define OPENED 2 /* Device opened */
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#define RXRDY 4
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#define TXCOMP 8
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#define TXRDY 0x10
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struct cdev *cdev;
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bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
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bus_dmamap_t map[4]; /* Maps for the transaction */
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};
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static inline uint32_t
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@ -77,7 +75,6 @@ WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val)
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#define AT91_SPI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define AT91_SPI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
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#define AT91_SPI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
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#define CDEV2SOFTC(dev) ((dev)->si_drv1)
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static devclass_t at91_spi_devclass;
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@ -86,25 +83,11 @@ static devclass_t at91_spi_devclass;
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static int at91_spi_probe(device_t dev);
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static int at91_spi_attach(device_t dev);
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static int at91_spi_detach(device_t dev);
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static void at91_spi_intr(void *);
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/* helper routines */
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static int at91_spi_activate(device_t dev);
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static void at91_spi_deactivate(device_t dev);
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/* cdev routines */
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static d_open_t at91_spi_open;
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static d_close_t at91_spi_close;
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static d_ioctl_t at91_spi_ioctl;
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static struct cdevsw at91_spi_cdevsw =
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{
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.d_version = D_VERSION,
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.d_open = at91_spi_open,
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.d_close = at91_spi_close,
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.d_ioctl = at91_spi_ioctl
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};
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static int
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at91_spi_probe(device_t dev)
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{
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@ -116,7 +99,7 @@ static int
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at91_spi_attach(device_t dev)
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{
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struct at91_spi_softc *sc = device_get_softc(dev);
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int err;
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int err, i;
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sc->dev = dev;
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err = at91_spi_activate(dev);
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@ -126,31 +109,45 @@ at91_spi_attach(device_t dev)
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AT91_SPI_LOCK_INIT(sc);
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/*
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* Activate the interrupt
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* Allocate DMA tags and maps
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*/
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err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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at91_spi_intr, sc, &sc->intrhand);
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if (err) {
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AT91_SPI_LOCK_DESTROY(sc);
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err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
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BUS_SPACE_MAXADDR, NULL, NULL, 2058, 1, 2048, BUS_DMA_ALLOCNOW,
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NULL, NULL, &sc->dmatag);
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if (err != 0)
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goto out;
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for (i = 0; i < 4; i++) {
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err = bus_dmamap_create(sc->dmatag, 0, &sc->map[i]);
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if (err != 0)
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goto out;
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}
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sc->cdev = make_dev(&at91_spi_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600,
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"spi%d", device_get_unit(dev));
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if (sc->cdev == NULL) {
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err = ENOMEM;
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goto out;
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}
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sc->cdev->si_drv1 = sc;
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#if 0
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/* init */
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sc->cwgr = SPI_CWGR_CKDIV(1) |
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SPI_CWGR_CHDIV(SPI_CWGR_DIV(SPI_DEF_CLK)) |
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SPI_CWGR_CLDIV(SPI_CWGR_DIV(SPI_DEF_CLK));
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// reset the SPI
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WR4(sc, SPI_CR, SPI_CR_SWRST);
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WR4(sc, SPI_CR, SPI_CR_MSEN | SPI_CR_SVDIS);
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WR4(sc, SPI_CWGR, sc->cwgr);
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#endif
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WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS |
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(0xE << 16));
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WR4(sc, SPI_CSR0, SPI_CSR_CPOL | (4 << 16) | (2 << 8));
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WR4(sc, SPI_CR, SPI_CR_SPIEN);
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WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS);
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WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS);
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WR4(sc, PDC_RNPR, 0);
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WR4(sc, PDC_RNCR, 0);
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WR4(sc, PDC_TNPR, 0);
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WR4(sc, PDC_TNCR, 0);
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WR4(sc, PDC_RPR, 0);
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WR4(sc, PDC_RCR, 0);
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WR4(sc, PDC_TPR, 0);
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WR4(sc, PDC_TCR, 0);
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WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
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WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
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RD4(sc, SPI_RDR);
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RD4(sc, SPI_SR);
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device_add_child(dev, "spibus", -1);
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bus_generic_attach(dev);
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out:;
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if (err)
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at91_spi_deactivate(dev);
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@ -208,229 +205,70 @@ at91_spi_deactivate(device_t dev)
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}
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static void
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at91_spi_intr(void *xsc)
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at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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{
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struct at91_spi_softc *sc = xsc;
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#if 0
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uint32_t status;
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/* Reading the status also clears the interrupt */
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status = RD4(sc, SPI_SR);
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if (status == 0)
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if (error != 0)
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return;
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AT91_SPI_LOCK(sc);
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if (status & SPI_SR_RXRDY)
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sc->flags |= RXRDY;
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if (status & SPI_SR_TXCOMP)
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sc->flags |= TXCOMP;
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if (status & SPI_SR_TXRDY)
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sc->flags |= TXRDY;
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AT91_SPI_UNLOCK(sc);
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#endif
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wakeup(sc);
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return;
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}
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static int
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at91_spi_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
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{
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struct at91_spi_softc *sc;
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sc = CDEV2SOFTC(dev);
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AT91_SPI_LOCK(sc);
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if (!(sc->flags & OPENED)) {
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sc->flags |= OPENED;
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#if 0
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WR4(sc, SPI_IER, SPI_SR_TXCOMP | SPI_SR_RXRDY | SPI_SR_TXRDY |
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SPI_SR_OVRE | SPI_SR_UNRE | SPI_SR_NACK);
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#endif
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}
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AT91_SPI_UNLOCK(sc);
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return (0);
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*(bus_addr_t *)arg = segs[0].ds_addr;
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}
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static int
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at91_spi_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
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at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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struct at91_spi_softc *sc;
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int i;
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bus_addr_t addr;
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sc = CDEV2SOFTC(dev);
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AT91_SPI_LOCK(sc);
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sc->flags &= ~OPENED;
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#if 0
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WR4(sc, SPI_IDR, SPI_SR_TXCOMP | SPI_SR_RXRDY | SPI_SR_TXRDY |
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SPI_SR_OVRE | SPI_SR_UNRE | SPI_SR_NACK);
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#endif
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AT91_SPI_UNLOCK(sc);
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sc = device_get_softc(dev);
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WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
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i = 0;
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if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_cmd,
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cmd->tx_cmd_sz, at91_getaddr, &addr, 0) != 0)
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goto out;
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WR4(sc, PDC_TPR, addr);
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WR4(sc, PDC_TCR, cmd->tx_cmd_sz);
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bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE);
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i++;
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if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_data,
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cmd->tx_data_sz, at91_getaddr, &addr, 0) != 0)
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goto out;
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WR4(sc, PDC_TNPR, addr);
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WR4(sc, PDC_TNCR, cmd->tx_cmd_sz);
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bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE);
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i++;
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if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_cmd,
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cmd->tx_cmd_sz, at91_getaddr, &addr, 0) != 0)
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goto out;
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WR4(sc, PDC_RPR, addr);
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WR4(sc, PDC_RCR, cmd->tx_cmd_sz);
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bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD);
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i++;
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if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_data,
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cmd->tx_data_sz, at91_getaddr, &addr, 0) != 0)
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goto out;
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WR4(sc, PDC_RNPR, addr);
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WR4(sc, PDC_RNCR, cmd->tx_data_sz);
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bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD);
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WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN);
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// wait for completion
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// XXX should be done as an ISR of some sort.
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while (RD4(sc, SPI_SR) & SPI_SR_ENDRX)
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DELAY(700);
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// Sync the buffers after the DMA is done, and unload them.
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bus_dmamap_sync(sc->dmatag, sc->map[0], BUS_DMASYNC_POSTWRITE);
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bus_dmamap_sync(sc->dmatag, sc->map[1], BUS_DMASYNC_POSTWRITE);
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bus_dmamap_sync(sc->dmatag, sc->map[2], BUS_DMASYNC_POSTREAD);
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bus_dmamap_sync(sc->dmatag, sc->map[3], BUS_DMASYNC_POSTREAD);
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for (i = 0; i < 4; i++)
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bus_dmamap_unload(sc->dmatag, sc->map[i]);
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return (0);
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}
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static int
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at91_spi_read_master(struct at91_spi_softc *sc, struct at91_spi_io *xfr)
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{
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#if 1
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return ENOTTY;
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#else
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uint8_t *walker;
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uint8_t buffer[256];
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size_t len;
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int err = 0;
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if (xfr->xfer_len > sizeof(buffer))
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return (EINVAL);
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walker = buffer;
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len = xfr->xfer_len;
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RD4(sc, SPI_RHR);
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// Master mode, with the right address and interal addr size
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WR4(sc, SPI_MMR, SPI_MMR_IADRSZ(xfr->iadrsz) | SPI_MMR_MREAD |
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SPI_MMR_DADR(xfr->dadr));
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WR4(sc, SPI_IADR, xfr->iadr);
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WR4(sc, SPI_CR, SPI_CR_START);
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while (len-- > 1) {
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while (!(sc->flags & RXRDY)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "spird",
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0);
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if (err)
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return (err);
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}
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sc->flags &= ~RXRDY;
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*walker++ = RD4(sc, SPI_RHR) & 0xff;
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}
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WR4(sc, SPI_CR, SPI_CR_STOP);
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while (!(sc->flags & TXCOMP)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "spird2", 0);
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if (err)
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return (err);
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}
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sc->flags &= ~TXCOMP;
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*walker = RD4(sc, SPI_RHR) & 0xff;
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if (xfr->xfer_buf) {
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AT91_SPI_UNLOCK(sc);
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err = copyout(buffer, xfr->xfer_buf, xfr->xfer_len);
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AT91_SPI_LOCK(sc);
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}
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return (err);
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#endif
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}
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static int
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at91_spi_write_master(struct at91_spi_softc *sc, struct at91_spi_io *xfr)
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{
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#if 1
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return ENOTTY;
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#else
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uint8_t *walker;
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uint8_t buffer[256];
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size_t len;
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int err;
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if (xfr->xfer_len > sizeof(buffer))
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return (EINVAL);
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walker = buffer;
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len = xfr->xfer_len;
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AT91_SPI_UNLOCK(sc);
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err = copyin(xfr->xfer_buf, buffer, xfr->xfer_len);
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AT91_SPI_LOCK(sc);
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if (err)
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return (err);
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/* Setup the xfr for later readback */
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xfr->xfer_buf = 0;
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xfr->xfer_len = 1;
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while (len--) {
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WR4(sc, SPI_MMR, SPI_MMR_IADRSZ(xfr->iadrsz) | SPI_MMR_MWRITE |
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SPI_MMR_DADR(xfr->dadr));
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WR4(sc, SPI_IADR, xfr->iadr++);
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WR4(sc, SPI_THR, *walker++);
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WR4(sc, SPI_CR, SPI_CR_START);
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/*
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* If we get signal while waiting for TXRDY, make sure we
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* try to stop this device
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*/
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while (!(sc->flags & TXRDY)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "spiwr",
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0);
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if (err)
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break;
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}
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WR4(sc, SPI_CR, SPI_CR_STOP);
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if (err)
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return (err);
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while (!(sc->flags & TXCOMP)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "spiwr2",
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0);
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if (err)
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return (err);
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}
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/* Readback */
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at91_spi_read_master(sc, xfr);
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}
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return (err);
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#endif
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}
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static int
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at91_spi_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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struct thread *td)
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{
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int err = 0;
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struct at91_spi_softc *sc;
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sc = CDEV2SOFTC(dev);
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AT91_SPI_LOCK(sc);
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while (sc->flags & XFER_PENDING) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH,
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"spiwait", 0);
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if (err) {
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AT91_SPI_UNLOCK(sc);
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return (err);
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}
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}
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sc->flags |= XFER_PENDING;
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switch (cmd)
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{
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case SPIIOCXFER:
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{
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struct at91_spi_io *xfr = (struct at91_spi_io *)data;
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switch (xfr->type)
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{
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case SPI_IO_READ_MASTER:
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err = at91_spi_read_master(sc, xfr);
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break;
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case SPI_IO_WRITE_MASTER:
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err = at91_spi_write_master(sc, xfr);
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break;
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default:
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err = EINVAL;
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break;
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}
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break;
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}
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case SPIIOCSETCLOCK:
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{
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#if 0
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struct at91_spi_clock *spick = (struct at91_spi_clock *)data;
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sc->cwgr = SPI_CWGR_CKDIV(spick->ckdiv) |
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SPI_CWGR_CHDIV(SPI_CWGR_DIV(spick->high_rate)) |
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SPI_CWGR_CLDIV(SPI_CWGR_DIV(spick->low_rate));
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WR4(sc, SPI_CR, SPI_CR_SWRST);
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WR4(sc, SPI_CR, SPI_CR_MSEN | SPI_CR_SVDIS);
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WR4(sc, SPI_CWGR, sc->cwgr);
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#else
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err = ENOTTY;
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#endif
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break;
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}
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default:
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err = ENOTTY;
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break;
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}
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sc->flags &= ~XFER_PENDING;
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AT91_SPI_UNLOCK(sc);
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wakeup(sc);
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return err;
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out:;
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while (i-- > 0)
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bus_dmamap_unload(sc->dmatag, sc->map[i]);
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return (EIO);
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}
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static device_method_t at91_spi_methods[] = {
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@ -439,6 +277,8 @@ static device_method_t at91_spi_methods[] = {
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DEVMETHOD(device_attach, at91_spi_attach),
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DEVMETHOD(device_detach, at91_spi_detach),
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||||
|
||||
/* spibus interface */
|
||||
DEVMETHOD(spibus_transfer, at91_spi_transfer),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
|
||||
@ -1,61 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2006 M. Warner Losh. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _ARM_AT91_AT91_SPIIO_H
|
||||
#define _ARM_AT91_AT91_SPIIO_H
|
||||
|
||||
#include <sys/ioccom.h>
|
||||
|
||||
struct at91_spi_io
|
||||
{
|
||||
int dadr; /* Device address */
|
||||
int type; /* read/write */
|
||||
#define SPI_IO_READ_MASTER 1
|
||||
#define SPI_IO_WRITE_MASTER 2
|
||||
int iadrsz; /* Internal addr size */
|
||||
uint32_t iadr; /* Interbak addr */
|
||||
size_t xfer_len; /* Size to transfer */
|
||||
caddr_t xfer_buf; /* buffer for xfer */
|
||||
};
|
||||
|
||||
struct at91_spi_clock
|
||||
{
|
||||
int ckdiv; /* Clock divider */
|
||||
int high_rate; /* rate of clock high period */
|
||||
int low_rate; /* rate of clock low period */
|
||||
};
|
||||
|
||||
/** SPIIOCXFER: Do a two-wire transfer
|
||||
*/
|
||||
#define SPIIOCXFER _IOW('x', 1, struct at91_spi_io)
|
||||
|
||||
/** SPIIOCSETCLOCK: Sets the clocking parameters for this operation.
|
||||
*/
|
||||
#define SPIIOCSETCLOCK _IOW('x', 2, struct at91_spi_clock)
|
||||
|
||||
#endif /* !_ARM_AT91_AT91_SPIIO_H */
|
||||
|
||||
|
||||
@ -27,4 +27,40 @@
|
||||
#ifndef ARM_AT91_AT91_SPIREG_H
|
||||
#define ARM_AT91_AT91_SPIREG_H
|
||||
|
||||
#define SPI_CR 0x00 /* CR: Control Register */
|
||||
#define SPI_CR_SPIEN 0x1
|
||||
#define SPI_CR_SPIDIS 0x2
|
||||
#define SPI_CR_SWRST 0x8
|
||||
#define SPI_MR 0x04 /* MR: Mode Register */
|
||||
#define SPI_MR_MSTR 0x01
|
||||
#define SPI_MR_PS 0x02
|
||||
#define SPI_MR_PCSDEC 0x04
|
||||
#define SPI_MR_DIV32 0x08
|
||||
#define SPI_MR_MODFDIS 0x10
|
||||
#define SPI_MR_LLB 0x80
|
||||
#define SPI_MR_PSC_CS0 0xe0000
|
||||
#define SPI_MR_PSC_CS1 0xd0000
|
||||
#define SPI_MR_PSC_CS2 0xb0000
|
||||
#define SPI_MR_PSC_CS3 0x70000
|
||||
#define SPI_RDR 0x08 /* RDR: Receive Data Register */
|
||||
#define SPI_TDR 0x0c /* TDR: Transmit Data Register */
|
||||
#define SPI_SR 0x10 /* SR: Status Register */
|
||||
#define SPI_SR_RDRF 0x00001
|
||||
#define SPI_SR_TDRE 0x00002
|
||||
#define SPI_SR_MODF 0x00004
|
||||
#define SPI_SR_OVRES 0x00008
|
||||
#define SPI_SR_ENDRX 0x00010
|
||||
#define SPI_SR_ENDTX 0x00020
|
||||
#define SPI_SR_RXBUFE 0x00040
|
||||
#define SPI_SR_TXBUFE 0x00080
|
||||
#define SPI_SR_SPIENS 0x10000
|
||||
#define SPI_IER 0x14 /* IER: Interrupt Enable Regsiter */
|
||||
#define SPI_IDR 0x18 /* IDR: Interrupt Disable Regsiter */
|
||||
#define SPI_IMR 0x1c /* IMR: Interrupt Mask Regsiter */
|
||||
#define SPI_CSR0 0x30 /* CS0: Chip Select 0 */
|
||||
#define SPI_CSR_CPOL 0x01
|
||||
#define SPI_CSR1 0x34 /* CS1: Chip Select 1 */
|
||||
#define SPI_CSR2 0x38 /* CS2: Chip Select 2 */
|
||||
#define SPI_CSR3 0x3c /* CS3: Chip Select 3 */
|
||||
|
||||
#endif /* ARM_AT91_AT91_SPIREG_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user