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- Do not enumerate PCIe bus on CN56XX Pass 1 devices to avoid hard hang.

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There is known issue with this hardware.

Submitted by:	Andrew Duane <aduane@juniper.net>
This commit is contained in:
Oleksandr Tymoshenko 2012-01-13 02:33:55 +00:00
parent 47b3924be0
commit 234f7fd5a3
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=230040
1 changed files with 6 additions and 0 deletions
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6
sys/contrib/octeon-sdk/cvmx-pcie.c
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@ -501,6 +501,12 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
}
}
/* Make sure a CN56XX pass 1 isn't trying to do anything; errata for PASS 1 */
if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) {
cvmx_dprintf ("PCIe port %d: CN56XX_PASS_1, skipping\n", pcie_port);
return -1;
}
/* PCIe switch arbitration mode. '0' == fixed priority NPEI, PCIe0, then PCIe1. '1' == round robin. */
npei_ctl_status.s.arb = 1;
/* Allow up to 0x20 config retries */