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Code Issues Releases Activity

* Add wireless MAC reset, in prep for bringing over AR9130 support.

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* Whilst I'm here, reformat to fit inside 80 characters.
This commit is contained in:
Adrian Chadd 2011-03-13 08:46:58 +00:00
parent c55baa23d8
commit 23dcc4c655
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=219592
1 changed files with 15 additions and 4 deletions
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19
sys/mips/atheros/ar91xx_chip.c
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@ -130,10 +130,12 @@ ar91xx_chip_set_pll_ge0(int speed)
pll = AR91XX_PLL_VAL_1000; pll = AR91XX_PLL_VAL_1000;
break; break;
default: default:
printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n", speed); printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
speed);
return; return;
} }
ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, AR91XX_ETH0_PLL_SHIFT); ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, AR91XX_ETH0_PLL_SHIFT);
} }
static void static void
@ -152,10 +154,12 @@ ar91xx_chip_set_pll_ge1(int speed)
pll = AR91XX_PLL_VAL_1000; pll = AR91XX_PLL_VAL_1000;
break; break;
default: default:
printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n", speed); printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
speed);
return; return;
} }
ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, AR91XX_ETH1_PLL_SHIFT); ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, AR91XX_ETH1_PLL_SHIFT);
} }
static void static void
@ -187,6 +191,13 @@ ar91xx_chip_init_usb_peripheral(void)
ar71xx_device_start(RST_RESET_USB_PHY); ar71xx_device_start(RST_RESET_USB_PHY);
DELAY(100); DELAY(100);
/* Wireless */
ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
DELAY(1000);
ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
DELAY(1000);
} }
struct ar71xx_cpu_def ar91xx_chip_def = { struct ar71xx_cpu_def ar91xx_chip_def = {