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Code Issues Releases Activity

Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernet

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switch reset/initialise functions.

The AR934x and QC955x SoCs both have a configurable MDIO base clock.
The others have the MDIO clock use the same clock as the system
reference clock, whatever that may be.

Tested:

* AR9344 SoC

TODO:

* mips24k - AR933x would be fine for now, just to ensure that things
  are sane.
This commit is contained in:
Adrian Chadd 2013-10-15 01:35:48 +00:00
parent 7e57b3ad31
commit 2418402399
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=256487
4 changed files with 30 additions and 3 deletions
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3
sys/mips/atheros/ar71xx_chip.c
View File

@ -81,6 +81,7 @@ uint32_t u_ar71xx_ddr_freq;
uint32_t u_ar71xx_uart_freq;
uint32_t u_ar71xx_wdt_freq;
uint32_t u_ar71xx_refclk;
uint32_t u_ar71xx_mdio_freq;
static void
ar71xx_chip_detect_mem_size(void)
@ -94,7 +95,7 @@ ar71xx_chip_detect_sys_frequency(void)
uint32_t freq;
uint32_t div;
u_ar71xx_refclk = AR71XX_BASE_FREQ;
u_ar71xx_mdio_freq = u_ar71xx_refclk = AR71XX_BASE_FREQ;
pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);

26
sys/mips/atheros/ar71xx_cpudef.h
View File

@ -57,6 +57,12 @@ struct ar71xx_cpu_def {
* each chip.
*/
void (* ar71xx_chip_init_usb_peripheral) (void);
void (* ar71xx_chip_reset_ethernet_switch) (void);
void (* ar71xx_chip_reset_wmac) (void);
void (* ar71xx_chip_init_gmac) (void);
};
extern struct ar71xx_cpu_def * ar71xx_cpu_ops;
@ -111,6 +117,24 @@ static inline void ar71xx_init_usb_peripheral(void)
ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral();
}
static inline void ar71xx_reset_ethernet_switch(void)
{
if (ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch)
ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch();
}
static inline void ar71xx_reset_wmac(void)
{
if (ar71xx_cpu_ops->ar71xx_chip_reset_wmac)
ar71xx_cpu_ops->ar71xx_chip_reset_wmac();
}
static inline void ar71xx_init_gmac(void)
{
if (ar71xx_cpu_ops->ar71xx_chip_init_gmac)
ar71xx_cpu_ops->ar71xx_chip_init_gmac();
}
static inline void ar71xx_device_ddr_flush_ip2(void)
{
ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2();
@ -123,6 +147,7 @@ extern uint32_t u_ar71xx_ahb_freq;
extern uint32_t u_ar71xx_ddr_freq;
extern uint32_t u_ar71xx_uart_freq;
extern uint32_t u_ar71xx_wdt_freq;
extern uint32_t u_ar71xx_mdio_freq;
static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; }
static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; }
@ -130,5 +155,6 @@ static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; }
static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; }
static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; }
static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; }
static inline uint64_t ar71xx_mdio_freq(void) { return u_ar71xx_mdio_freq; }
#endif

2
sys/mips/atheros/ar724x_chip.c
View File

@ -73,7 +73,7 @@ ar724x_chip_detect_sys_frequency(void)
uint32_t freq;
uint32_t div;
u_ar71xx_refclk = AR724X_BASE_FREQ;
u_ar71xx_mdio_freq = u_ar71xx_refclk = AR724X_BASE_FREQ;
pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);

2
sys/mips/atheros/ar91xx_chip.c
View File

@ -71,7 +71,7 @@ ar91xx_chip_detect_sys_frequency(void)
uint32_t freq;
uint32_t div;
u_ar71xx_refclk = AR91XX_BASE_FREQ;
u_ar71xx_mdio_freq = u_ar71xx_refclk = AR91XX_BASE_FREQ;
pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);