mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-19 10:53:58 +00:00
Move interrupt enable into the OSM.
Set the AHC_LSCBS_ENABLED softc flag appropriately. Convert to using softc storage for our seeprom data. Break seeprom parsing out into a separate routine. Change our policy in regards to AHC_SPIOCAP so that we will allow auto-termination to take place on some aic7855 based cards. Remove initialized but never really used variables.
This commit is contained in:
Justin T. Gibbs
parent
4c4797e6b4
commit
274c41275c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=102676
@ -39,7 +39,7 @@
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGES.
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*
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* $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#37 $
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* $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#50 $
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*
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* $FreeBSD$
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*/
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@ -667,6 +667,8 @@ static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
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int pcheck, int fast, int large);
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static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
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static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
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static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
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struct seeprom_config *sc);
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static void configure_termination(struct ahc_softc *ahc,
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struct seeprom_descriptor *sd,
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u_int adapter_control,
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@ -769,16 +771,16 @@ ahc_find_pci_device(ahc_dev_softc_t pci)
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int
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ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
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{
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struct scb_data *shared_scb_data;
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u_int command;
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u_int our_id = 0;
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u_int sxfrctl1;
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u_int scsiseq;
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u_int dscommand0;
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int error;
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uint8_t sblkctl;
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u_long l;
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u_int command;
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u_int our_id;
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u_int sxfrctl1;
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u_int scsiseq;
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u_int dscommand0;
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int error;
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uint8_t sblkctl;
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shared_scb_data = NULL;
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our_id = 0;
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error = entry->setup(ahc);
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if (error != 0)
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return (error);
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@ -974,11 +976,6 @@ ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
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if (error != 0)
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return (error);
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/*
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* Link this softc in with all other ahc instances.
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*/
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ahc_softc_insert(ahc);
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/*
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* Allow interrupts now that we are completely setup.
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*/
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@ -986,8 +983,12 @@ ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
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if (error != 0)
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return (error);
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ahc_intr_enable(ahc, TRUE);
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ahc_list_lock(&l);
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/*
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* Link this softc in with all other ahc instances.
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*/
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ahc_softc_insert(ahc);
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ahc_list_unlock(&l);
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return (0);
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}
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@ -1045,6 +1046,9 @@ ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
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ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
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}
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ahc->flags &= ~AHC_LSCBS_ENABLED;
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if (large)
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ahc->flags |= AHC_LSCBS_ENABLED;
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devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
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if ((ahc->features & AHC_ULTRA2) != 0) {
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u_int dscommand0;
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@ -1191,9 +1195,7 @@ static void
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check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
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{
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struct seeprom_descriptor sd;
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struct seeprom_config sc;
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u_int scsi_conf;
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u_int adapter_control;
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struct seeprom_config *sc;
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int have_seeprom;
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int have_autoterm;
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@ -1201,6 +1203,7 @@ check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
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sd.sd_control_offset = SEECTL;
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sd.sd_status_offset = SEECTL;
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sd.sd_dataout_offset = SEECTL;
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sc = ahc->seep_config;
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/*
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* For some multi-channel devices, the c46 is simply too
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@ -1231,12 +1234,12 @@ check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
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start_addr = 32 * (ahc->channel - 'A');
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have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)&sc,
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have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
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start_addr,
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sizeof(sc)/2);
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sizeof(*sc)/2);
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if (have_seeprom)
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have_seeprom = ahc_verify_cksum(&sc);
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have_seeprom = ahc_verify_cksum(sc);
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if (have_seeprom != 0 || sd.sd_chip == C56_66) {
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if (bootverbose) {
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@ -1268,16 +1271,17 @@ check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
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uint16_t *sc_data;
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int i;
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sc_data = (uint16_t *)≻
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for (i = 0; i < 32; i++) {
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uint16_t val;
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int j;
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sc_data = (uint16_t *)sc;
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for (i = 0; i < 32; i++, sc_data++) {
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int j;
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j = i * 2;
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val = ahc_inb(ahc, SRAM_BASE + j)
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| ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
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*sc_data = ahc_inb(ahc, SRAM_BASE + j)
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| ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
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}
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have_seeprom = ahc_verify_cksum(&sc);
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have_seeprom = ahc_verify_cksum(sc);
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if (have_seeprom)
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ahc->flags |= AHC_SCB_CONFIG_USED;
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}
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/*
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* Clear any SCB parity errors in case this data and
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@ -1291,121 +1295,11 @@ check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
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if (bootverbose)
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printf("%s: No SEEPROM available.\n", ahc_name(ahc));
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ahc->flags |= AHC_USEDEFAULTS;
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free(ahc->seep_config, M_DEVBUF);
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ahc->seep_config = NULL;
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sc = NULL;
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} else {
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/*
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* Put the data we've collected down into SRAM
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* where ahc_init will find it.
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*/
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int i;
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int max_targ = sc.max_targets & CFMAXTARG;
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uint16_t discenable;
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uint16_t ultraenb;
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discenable = 0;
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ultraenb = 0;
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if ((sc.adapter_control & CFULTRAEN) != 0) {
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/*
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* Determine if this adapter has a "newstyle"
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* SEEPROM format.
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*/
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for (i = 0; i < max_targ; i++) {
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if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){
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ahc->flags |= AHC_NEWEEPROM_FMT;
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break;
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}
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}
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}
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for (i = 0; i < max_targ; i++) {
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u_int scsirate;
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uint16_t target_mask;
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target_mask = 0x01 << i;
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if (sc.device_flags[i] & CFDISC)
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discenable |= target_mask;
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if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
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if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0)
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ultraenb |= target_mask;
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} else if ((sc.adapter_control & CFULTRAEN) != 0) {
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ultraenb |= target_mask;
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}
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if ((sc.device_flags[i] & CFXFER) == 0x04
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&& (ultraenb & target_mask) != 0) {
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/* Treat 10MHz as a non-ultra speed */
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sc.device_flags[i] &= ~CFXFER;
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ultraenb &= ~target_mask;
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}
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if ((ahc->features & AHC_ULTRA2) != 0) {
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u_int offset;
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if (sc.device_flags[i] & CFSYNCH)
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offset = MAX_OFFSET_ULTRA2;
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else
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offset = 0;
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ahc_outb(ahc, TARG_OFFSET + i, offset);
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/*
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* The ultra enable bits contain the
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* high bit of the ultra2 sync rate
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* field.
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*/
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scsirate = (sc.device_flags[i] & CFXFER)
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| ((ultraenb & target_mask)
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? 0x8 : 0x0);
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if (sc.device_flags[i] & CFWIDEB)
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scsirate |= WIDEXFER;
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} else {
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scsirate = (sc.device_flags[i] & CFXFER) << 4;
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if (sc.device_flags[i] & CFSYNCH)
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scsirate |= SOFS;
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if (sc.device_flags[i] & CFWIDEB)
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scsirate |= WIDEXFER;
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}
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ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
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}
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ahc->our_id = sc.brtime_id & CFSCSIID;
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scsi_conf = (ahc->our_id & 0x7);
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if (sc.adapter_control & CFSPARITY)
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scsi_conf |= ENSPCHK;
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if (sc.adapter_control & CFRESETB)
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scsi_conf |= RESET_SCSI;
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ahc->flags |=
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(sc.adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
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if (sc.bios_control & CFEXTEND)
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ahc->flags |= AHC_EXTENDED_TRANS_A;
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if (sc.bios_control & CFBIOSEN)
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ahc->flags |= AHC_BIOS_ENABLED;
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if (ahc->features & AHC_ULTRA
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&& (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
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/* Should we enable Ultra mode? */
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if (!(sc.adapter_control & CFULTRAEN))
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/* Treat us as a non-ultra card */
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ultraenb = 0;
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}
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if (sc.signature == CFSIGNATURE
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|| sc.signature == CFSIGNATURE2) {
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uint32_t devconfig;
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/* Honor the STPWLEVEL settings */
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devconfig = ahc_pci_read_config(ahc->dev_softc,
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DEVCONFIG, /*bytes*/4);
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devconfig &= ~STPWLEVEL;
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if ((sc.bios_control & CFSTPWLEVEL) != 0)
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devconfig |= STPWLEVEL;
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ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
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devconfig, /*bytes*/4);
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}
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/* Set SCSICONF info */
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ahc_outb(ahc, SCSICONF, scsi_conf);
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ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
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ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
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ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
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ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
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ahc_parse_pci_eeprom(ahc, sc);
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}
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/*
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@ -1415,10 +1309,6 @@ check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
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* hasn't failed yet...
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*/
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have_autoterm = have_seeprom;
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if (have_seeprom)
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adapter_control = sc.adapter_control;
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else
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adapter_control = CFAUTOTERM;
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/*
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* Some low-cost chips have SEEPROM and auto-term control built
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@ -1426,19 +1316,143 @@ check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
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* if the termination logic is enabled.
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*/
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if ((ahc->features & AHC_SPIOCAP) != 0) {
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if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0)
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have_autoterm = TRUE;
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else
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if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
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have_autoterm = FALSE;
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}
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if (have_autoterm) {
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ahc_acquire_seeprom(ahc, &sd);
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configure_termination(ahc, &sd, adapter_control, sxfrctl1);
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configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
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ahc_release_seeprom(&sd);
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} else if (have_seeprom) {
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*sxfrctl1 &= ~STPWEN;
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if ((sc->adapter_control & CFSTERM) != 0)
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*sxfrctl1 |= STPWEN;
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if (bootverbose)
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printf("%s: Low byte termination %sabled\n",
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ahc_name(ahc),
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(*sxfrctl1 & STPWEN) ? "en" : "dis");
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}
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}
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static void
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ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
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{
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/*
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* Put the data we've collected down into SRAM
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* where ahc_init will find it.
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*/
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int i;
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int max_targ = sc->max_targets & CFMAXTARG;
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u_int scsi_conf;
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uint16_t discenable;
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uint16_t ultraenb;
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discenable = 0;
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ultraenb = 0;
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if ((sc->adapter_control & CFULTRAEN) != 0) {
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/*
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* Determine if this adapter has a "newstyle"
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* SEEPROM format.
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*/
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for (i = 0; i < max_targ; i++) {
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if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
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ahc->flags |= AHC_NEWEEPROM_FMT;
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break;
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}
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}
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}
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for (i = 0; i < max_targ; i++) {
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u_int scsirate;
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uint16_t target_mask;
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target_mask = 0x01 << i;
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if (sc->device_flags[i] & CFDISC)
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discenable |= target_mask;
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if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
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if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
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ultraenb |= target_mask;
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} else if ((sc->adapter_control & CFULTRAEN) != 0) {
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ultraenb |= target_mask;
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}
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if ((sc->device_flags[i] & CFXFER) == 0x04
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&& (ultraenb & target_mask) != 0) {
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/* Treat 10MHz as a non-ultra speed */
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sc->device_flags[i] &= ~CFXFER;
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ultraenb &= ~target_mask;
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}
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if ((ahc->features & AHC_ULTRA2) != 0) {
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u_int offset;
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if (sc->device_flags[i] & CFSYNCH)
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offset = MAX_OFFSET_ULTRA2;
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else
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offset = 0;
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ahc_outb(ahc, TARG_OFFSET + i, offset);
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/*
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* The ultra enable bits contain the
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* high bit of the ultra2 sync rate
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* field.
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*/
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scsirate = (sc->device_flags[i] & CFXFER)
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| ((ultraenb & target_mask) ? 0x8 : 0x0);
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if (sc->device_flags[i] & CFWIDEB)
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scsirate |= WIDEXFER;
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} else {
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scsirate = (sc->device_flags[i] & CFXFER) << 4;
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if (sc->device_flags[i] & CFSYNCH)
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scsirate |= SOFS;
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if (sc->device_flags[i] & CFWIDEB)
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scsirate |= WIDEXFER;
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}
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ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
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}
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ahc->our_id = sc->brtime_id & CFSCSIID;
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scsi_conf = (ahc->our_id & 0x7);
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if (sc->adapter_control & CFSPARITY)
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scsi_conf |= ENSPCHK;
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if (sc->adapter_control & CFRESETB)
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scsi_conf |= RESET_SCSI;
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ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
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if (sc->bios_control & CFEXTEND)
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ahc->flags |= AHC_EXTENDED_TRANS_A;
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if (sc->bios_control & CFBIOSEN)
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ahc->flags |= AHC_BIOS_ENABLED;
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if (ahc->features & AHC_ULTRA
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&& (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
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/* Should we enable Ultra mode? */
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if (!(sc->adapter_control & CFULTRAEN))
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/* Treat us as a non-ultra card */
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ultraenb = 0;
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}
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if (sc->signature == CFSIGNATURE
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|| sc->signature == CFSIGNATURE2) {
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uint32_t devconfig;
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/* Honor the STPWLEVEL settings */
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devconfig = ahc_pci_read_config(ahc->dev_softc,
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DEVCONFIG, /*bytes*/4);
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devconfig &= ~STPWLEVEL;
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if ((sc->bios_control & CFSTPWLEVEL) != 0)
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devconfig |= STPWLEVEL;
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ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
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devconfig, /*bytes*/4);
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}
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/* Set SCSICONF info */
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ahc_outb(ahc, SCSICONF, scsi_conf);
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ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
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ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
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ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
|
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ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
|
||||
}
|
||||
|
||||
static void
|
||||
configure_termination(struct ahc_softc *ahc,
|
||||
struct seeprom_descriptor *sd,
|
||||
@ -1479,10 +1493,10 @@ configure_termination(struct ahc_softc *ahc,
|
||||
enablePRI_high = 0;
|
||||
if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
|
||||
ahc_new_term_detect(ahc, &enableSEC_low,
|
||||
&enableSEC_high,
|
||||
&enablePRI_low,
|
||||
&enablePRI_high,
|
||||
&eeprom_present);
|
||||
&enableSEC_high,
|
||||
&enablePRI_low,
|
||||
&enablePRI_high,
|
||||
&eeprom_present);
|
||||
if ((adapter_control & CFSEAUTOTERM) == 0) {
|
||||
if (bootverbose)
|
||||
printf("%s: Manual SE Termination\n",
|
||||
@ -1506,6 +1520,8 @@ configure_termination(struct ahc_softc *ahc,
|
||||
aic785X_cable_detect(ahc, &internal50_present,
|
||||
&externalcable_present,
|
||||
&eeprom_present);
|
||||
/* Can never support a wide connector. */
|
||||
internal68_present = 0;
|
||||
} else {
|
||||
aic787X_cable_detect(ahc, &internal50_present,
|
||||
&internal68_present,
|
||||
@ -1731,7 +1747,12 @@ aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
|
||||
int *externalcable_present, int *eeprom_present)
|
||||
{
|
||||
uint8_t brdctl;
|
||||
uint8_t spiocap;
|
||||
|
||||
spiocap = ahc_inb(ahc, SPIOCAP);
|
||||
spiocap &= ~SOFTCMDEN;
|
||||
spiocap |= EXT_BRDCTL;
|
||||
ahc_outb(ahc, SPIOCAP, spiocap);
|
||||
ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
|
||||
ahc_outb(ahc, BRDCTL, 0);
|
||||
brdctl = ahc_inb(ahc, BRDCTL);
|
||||
@ -1927,10 +1948,8 @@ ahc_aic7860_setup(struct ahc_softc *ahc)
|
||||
static int
|
||||
ahc_apa1480_setup(struct ahc_softc *ahc)
|
||||
{
|
||||
ahc_dev_softc_t pci;
|
||||
int error;
|
||||
|
||||
pci = ahc->dev_softc;
|
||||
error = ahc_aic7860_setup(ahc);
|
||||
if (error != 0)
|
||||
return (error);
|
||||
@ -1941,9 +1960,7 @@ ahc_apa1480_setup(struct ahc_softc *ahc)
|
||||
static int
|
||||
ahc_aic7870_setup(struct ahc_softc *ahc)
|
||||
{
|
||||
ahc_dev_softc_t pci;
|
||||
|
||||
pci = ahc->dev_softc;
|
||||
ahc->channel = 'A';
|
||||
ahc->chip = AHC_AIC7870;
|
||||
ahc->features = AHC_AIC7870_FE;
|
||||
@ -2007,13 +2024,9 @@ ahc_aic7880_setup(struct ahc_softc *ahc)
|
||||
static int
|
||||
ahc_aha2940Pro_setup(struct ahc_softc *ahc)
|
||||
{
|
||||
ahc_dev_softc_t pci;
|
||||
int error;
|
||||
|
||||
pci = ahc->dev_softc;
|
||||
ahc->flags |= AHC_INT50_SPEEDFLEX;
|
||||
error = ahc_aic7880_setup(ahc);
|
||||
return (0);
|
||||
return (ahc_aic7880_setup(ahc));
|
||||
}
|
||||
|
||||
static int
|
||||
@ -2058,9 +2071,7 @@ ahc_aic7890_setup(struct ahc_softc *ahc)
|
||||
static int
|
||||
ahc_aic7892_setup(struct ahc_softc *ahc)
|
||||
{
|
||||
ahc_dev_softc_t pci;
|
||||
|
||||
pci = ahc->dev_softc;
|
||||
ahc->channel = 'A';
|
||||
ahc->chip = AHC_AIC7892;
|
||||
ahc->features = AHC_AIC7892_FE;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user